Patents by Inventor John Michael Cotte

John Michael Cotte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10199516
    Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.
    Type: Grant
    Filed: July 8, 2017
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Rob Steeman, Roland Yudadibrata Utama
  • Publication number: 20170309760
    Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.
    Type: Application
    Filed: July 8, 2017
    Publication date: October 26, 2017
    Inventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Rob Steeman, Roland Yudadibrata Utama
  • Patent number: 9716192
    Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Rob Steeman, Roland Yudadibrata Utama
  • Publication number: 20150325716
    Abstract: Photovoltaic devices are formed with electroplated metal grids that are effectively adhered to the devices. Metal-rich silicides, such as nickel silicides, are formed on the devices by annealing. The metal used in the anneal exhibits low stress. Annealing may be conducted in ambient air followed by removal of oxide and excess metal from the metal-rich silicide. Laser patterning of the antireflective coating of the devices can be used to expose the emitter to form front grid contacts. Doping of the emitter in the patterned region can be increased during laser patterning. The ratio of the centerline to centerline pitch per laser width is controlled to ensure sufficient adhesion of subsequently plated busbars.
    Type: Application
    Filed: March 19, 2015
    Publication date: November 12, 2015
    Inventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Hwee Meng Lam, Christian Lavoie, Xiaoyan Shao, Rob Steeman
  • Publication number: 20150280022
    Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.
    Type: Application
    Filed: March 19, 2015
    Publication date: October 1, 2015
    Inventors: Brett Caroline Baker-O'Neal, Shu-Yun Chong, John Michael Cotte, Ronald Dean Goldblatt, Jeffrey Hedrick, Qiang Huang, Susan Huang, Laura Louise Kosbar, Rob Steeman, Roland Yudadibrata Utama
  • Patent number: 8796138
    Abstract: Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machiness Corporation
    Inventors: John Michael Cotte, Christopher Vincent Jahnes, Bucknell Chapman Webb
  • Patent number: 8426316
    Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Nils Deneke Hoivik, Christopher Vincent Jahnes, Robert Luke Wisnieff
  • Patent number: 8338920
    Abstract: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Hanyi Ding, Kai Di Feng, Zhong-Xiang He, Nils D. Hoivik, Xuefeng Liu
  • Patent number: 8263492
    Abstract: Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: September 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Christopher Vincent Jahnes, Bucknell Chapman Webb
  • Publication number: 20120217651
    Abstract: Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal.
    Type: Application
    Filed: May 10, 2012
    Publication date: August 30, 2012
    Applicant: International Business Machines Corporation
    Inventors: John Michael Cotte, Christopher Vincent Jahnes, Bucknell Chapman Webb
  • Patent number: 7863189
    Abstract: Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with low defect density. In particular, methods are provided which enable fabrication of silicon carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghaven S. Basker, John Michael Cotte, Hariklia Deligianni, John Ulrich Knickerbocker, Keith T. Kwietniak
  • Publication number: 20100276786
    Abstract: Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 4, 2010
    Applicant: International Business Machines Corporation
    Inventors: John Michael Cotte, Christopher Vincent Jahnes, Bucknell Chapman Webb
  • Patent number: 7808798
    Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Brian Paul Gaucher, Janusz Grzyb, Nils Deneke Hoivik, Christopher Vincent Jahnes, John Ulrich Knickerbocker, Duixian Liu, John Harold Magerlein, Chirag Suryakant Patel, Ullrich R. Pfeiffer, Cornelia Kang-I Tsang
  • Patent number: 7518229
    Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: April 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Brian Paul Gaucher, Janusz Grzyb, Nils Deneke Hoivik, Christopher Vincent Jahnes, John Ulrich Knickerbocker, Duixian Liu, John Harold Magerlein, Chirag Suryakant Patel, Ullrich R. Pfeiffer, Cornelia Kang-I Tsang
  • Publication number: 20090001587
    Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
    Type: Application
    Filed: September 4, 2008
    Publication date: January 1, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Michael Cotte, Nils Deneke Hoivik, Christopher Vincent Jahnes, Robert Luke Wisnieff
  • Publication number: 20080277769
    Abstract: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.
    Type: Application
    Filed: May 8, 2007
    Publication date: November 13, 2008
    Inventors: John Michael Cotte, Hanyi Ding, Kai Di Feng, Zhong-Xiang He, Nils D. Hoivik, Xuefeng Liu
  • Patent number: 7422983
    Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: September 9, 2008
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Nils Deneke Hoivik, Christopher Vincent Jahnes, Robert Luke Wisnieff
  • Publication number: 20080186247
    Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.
    Type: Application
    Filed: April 4, 2008
    Publication date: August 7, 2008
    Applicant: International Business Machines Corporation
    Inventors: John Michael Cotte, Brian Paul Gaucher, Janusz Grzyb, Nils Deneke Hoivik, Christopher Vincent Jahnes, John Ulrich Knickerbocker, Duixian Liu, John Harold Magerlein, Chirag Suryakant Patel, Ullrich R. Pfeiffer
  • Publication number: 20080164573
    Abstract: Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with, low defect density. In particular, methods are provided which enable fabrication of silicon, carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Inventors: Veeraraghaven S. Basker, John Michael Cotte, Hariklia Deligianni, John Ulrich Knickerbocker, Keith T. Kwietniak
  • Patent number: 7332436
    Abstract: A composition which includes liquid or supercritical carbon dioxide and an acid having a pKa of less than about 4. The composition is employed in a process of removing residue from a precision surface, such as a semiconductor sample, in which the precision surface is contacted with the composition under thermodynamic conditions consistent with the retention of the liquid or supercritical carbon dioxide in the liquid or supercritical state.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: February 19, 2008
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Dario L. Goldfarb, Pamela Jones, Kenneth John McCullough, Wayne Martin Moreau, Keith R. Pope, John P. Simons, Charles J. Taft