Patents by Inventor John Nowak

John Nowak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622472
    Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 14, 2020
    Assignee: Monolith Semiconductor Inc.
    Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
  • Publication number: 20190334025
    Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 31, 2019
    Applicant: Monolith Semiconductor Inc.
    Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
  • Patent number: 10361296
    Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 23, 2019
    Assignee: Monolith Semiconductor Inc.
    Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
  • Publication number: 20190006505
    Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
  • Publication number: 20180141265
    Abstract: The subject matter described herein relates to methods and systems for fast imprinting of nanometer scale features in a workpiece. According to one aspect, a system for producing nanometer scale features in a workpiece is disclosed. The system includes a die having a surface with at least one nanometer scale feature located thereon. A first actuator moves the die with respect to the workpiece such that the at least one nanometer scale feature impacts the workpiece and imprints a corresponding at least one nanometer scale feature in the workpiece.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 24, 2018
    Inventors: Thomas A. Dow, Erik Zdanowicz, Alexander Sohn, Ron Scattergood, William John Nowak, JR.
  • Patent number: 9956720
    Abstract: The subject matter described herein relates to methods and systems for fast imprinting of nanometer scale features in a workpiece. According to one aspect, a system for producing nanometer scale features in a workpiece is disclosed. The system includes a die having a surface with at least one nanometer scale feature located thereon. A first actuator moves the die with respect to the workpiece such that the at least one nanometer scale feature impacts the workpiece and imprints a corresponding at least one nanometer scale feature in the workpiece.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 1, 2018
    Assignee: North Carolina State University
    Inventors: Thomas A. Dow, Erik Zdanowicz, Alexander Sohn, Ron Scattergood, William John Nowak, Jr.
  • Patent number: 9847154
    Abstract: Communication cable including insulated conductors and a composite tape having an insulative layer and a conductive layer. The composite tape includes first and second lateral sections that are folded over each other to form a shielding tape. The shielding tape includes opposite inner and outer sides that are formed from the first and second lateral sections, respectively, and a folded edge that joins the inner and outer sides. The conductive layer defines the inner side, the outer side, and the folded edge. The shielding tape is wrapped helically about the insulated conductors a plurality of times along a length of the communication cable to form a plurality of wraps. The inner side of a subsequent wrap of the shielding tape overlaps a portion of the outer side of a prior wrap of the shielding tape.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 19, 2017
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: Charles Lloyd Grant, Andrew John Nowak, Thomas Joseph Grzysiewicz, Paul Leo Grant, Roger Edward Temple, Victor William Lee, Rama Krishna Nippani
  • Publication number: 20170178989
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Application
    Filed: March 1, 2017
    Publication date: June 22, 2017
    Inventors: Kevin MATOCHA, John NOWAK, Kiran CHATTY, Sujit BANERJEE
  • Patent number: 9620428
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 11, 2017
    Assignee: MONOLITH SEMICONDUCTOR INC.
    Inventors: Kevin Matocha, John Nowak, Kiran Chatty, Sujit Banerjee
  • Publication number: 20160343631
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Application
    Filed: July 22, 2016
    Publication date: November 24, 2016
    Inventors: Kevin MATOCHA, John NOWAK, Kiran CHATTY, Sujit BANERJEE
  • Patent number: 9425153
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: August 23, 2016
    Assignee: MONOLITH SEMICONDUCTOR INC.
    Inventors: Kevin Matocha, John Nowak, Kiran Chatty, Sujit Banerjee
  • Publication number: 20160064119
    Abstract: Communication cable including insulated conductors and a composite tape having an insulative layer and a conductive layer. The composite tape includes first and second lateral sections that are folded over each other to form a shielding tape. The shielding tape includes opposite inner and outer sides that are formed from the first and second lateral sections, respectively, and a folded edge that joins the inner and outer sides. The conductive layer defines the inner side, the outer side, and the folded edge. The shielding tape is wrapped helically about the insulated conductors a plurality of times along a length of the communication cable to form a plurality of wraps. The inner side of a subsequent wrap of the shielding tape overlaps a portion of the outer side of a prior wrap of the shielding tape.
    Type: Application
    Filed: October 27, 2014
    Publication date: March 3, 2016
    Inventors: Charles Lloyd Grant, Andrew John Nowak, Thomas Joseph Grzysiewicz, Paul Leo Grant, Roger Edward Temple, Victor William Lee, Rama Krishna Nippani
  • Publication number: 20150239172
    Abstract: The subject matter described herein relates to methods and systems for fast imprinting of nanometer scale features in a workpiece. According to one aspect, a system for producing nanometer scale features in a workpiece is disclosed. The system includes a die having a surface with at least one nanometer scale feature located thereon. A first actuator moves the die with respect to the workpiece such that the at least one nanometer scale feature impacts the workpiece and imprints a corresponding at least one nanometer scale feature in the workpiece.
    Type: Application
    Filed: September 27, 2013
    Publication date: August 27, 2015
    Inventors: Thomas A. Dow, Erik Zdanowicz, Alexander Sohn, Ron Scattergood, William John Nowak, JR.
  • Publication number: 20150214164
    Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Inventors: Kevin MATOCHA, John NOWAK, Kiran CHATTY, Sujit BANERJEE
  • Patent number: 8981216
    Abstract: A cable assembly includes elongated conductors, primary dielectric layers, a secondary dielectric layer, a conductive shield layer and a drain wire. The conductors communicate a signal. The primary dielectric layer is circumferentially disposed around each of the conductors. The secondary dielectric layer surrounds the primary dielectric layers. The conductive shield layer is disposed around the secondary dielectric layer. The drain wire is provided along an outer surface of the conductive shield layer and is electrically coupled with the conductive shield layer. The conductive shield layer communicates electromagnetic interference to an electric ground reference via the drain wire.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 17, 2015
    Assignee: Tyco Electronics Corporation
    Inventors: Charles Lloyd Grant, Edward Young, Andrew John Nowak, Thomas Joseph Grzysiewicz, Paul Leo Grant, Kevan Tran
  • Publication number: 20110315419
    Abstract: A cable assembly includes elongated conductors, primary dielectric layers, a secondary dielectric layer, a conductive shield layer and a drain wire. The conductors communicate a signal. The primary dielectric layer is circumferentially disposed around each of the conductors. The secondary dielectric layer surrounds the primary dielectric layers. The conductive shield layer is disposed around the secondary dielectric layer. The drain wire is provided along an outer surface of the conductive shield layer and is electrically coupled with the conductive shield layer. The conductive shield layer communicates electromagnetic interference to an electric ground reference via the drain wire.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: Tyco Electronics Corporation
    Inventors: Charles Lloyd Grant, Edward Young, Andrew John Nowak, Thomas Joseph Grzysiewicz, Paul Leo Grant, Kevan Tran
  • Patent number: 7326814
    Abstract: The present invention relates to a process for the minimization of volatile organic sulphur byproducts in dimethyl sulfate quaternization of amines made with hypophosphorous acid, which leads to the formation of an odor stable product.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: February 5, 2008
    Assignee: Akzo Nobel N.V.
    Inventors: Elliot Band, Maurice Dery, William Joyce, Jeffrey Earl Telschow, Biing Ming Su, Michael Engel, John Nowak, Claude Peterson, Harold Providence, Phuong-Nga Trinh, Sandra Urquhart
  • Publication number: 20070099245
    Abstract: This invention relates to assays for the detection of neutralizing antibodies. Further, this invention relates to assays for the detection of neutralizing antibodies specific for bone morphogenetic protein 2 (BMP-2) or capable of inhibiting at least one of the biological activities of BMP-2.
    Type: Application
    Filed: September 29, 2006
    Publication date: May 3, 2007
    Inventors: Boris Gorovits, John Nowak, Denise O'Hara, William Dickerson, Tony Celeste
  • Publication number: 20060240487
    Abstract: Methods to detect GDF-8 modulating agents in animals, including humans, are provided herein, including methods to detect the presence of exogenous GDF-8 modulating agent such as a GDF-8 inhibitor in a biological sample. In particular, methods to assess the presence and/or quantity of a GDF-8 modulating agent in a biological sample are provided.
    Type: Application
    Filed: March 23, 2006
    Publication date: October 26, 2006
    Inventors: John Nowak, John Cryan, Kristin Murray, Joseph Rajewski, Shujun Sun, Neil Wolfman
  • Publication number: 20060240488
    Abstract: This disclosure provides methods for the detection of antibodies to a GDF-8 modulating agent such as, e.g., MYO-029, in a biological sample. Methods to detect an immune response to a GDF-8 modulating agent are also included. In particular, methods to assess an immune response in animals, including humans, to a GDF-8 modulating agent such as a GDF-8 inhibitor are provided herein.
    Type: Application
    Filed: March 23, 2006
    Publication date: October 26, 2006
    Inventors: John Nowak, Denise O'Hara, John Cryan, Teresa Caiazzo, Alison Joyce, Joseph Rajewski, Shujun Sun, Neil Wolfman