Abstract: A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.

Abstract: A spaced, bumped component structure including a first plate, a second plate spaced from the first plate by a first gap, a plurality of solder bumps interconnecting the plates and defining the first gap; at least one of the plates having an anomalous section including one of a raised platform and recess for defining a second gap having a different size from the first gap.

Abstract: A method and apparatus for communicating message data between a plurality of subsystems (201, 202, 301, 302, 303, 404, 406, 408) in the form of distributed resource managers. The subsystems are coupled together through a coupling means (206, 306, 410) with a shared memory with at least one shared queue (308, 414) in the shared memory. Access to the shared queue (308, 414) is available from each of the coupled subsystems and message data can be communicated between the subsystems via the shared queue (308, 414). Each subsystem has a long running process (304) checking the shared queue for messages for that subsystem.

Abstract: A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

Abstract: A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.

Abstract: Provided are methods, data communication apparatus and computer programs for managing communications between a remote communication manager and a set of communications managers in an associated group. The group of communication managers have shared access to resources which enable any communication manager in the group to recover from failures experienced by another communication manager in the group. In particular, recovery of failed inbound and outbound channels is achieved with the advantage of improved availability of data transmissions. Preferably, the recovery uses synchronization information to ensure that data is recovered to a consistent state to that channel recovery is achieved without loss of data integrity.

Abstract: A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.

Abstract: Provided are a method and apparatus for providing serialization support for computer systems and computer system resources, in particular for application programs which require sequencing and/or consistency of data. The computer system resource includes serialized processes with units of work. A serialization token is provided at the start of a serialized process including at least one unit of work. The serialization token remains in force until the or all of the units of work of the process have been committed or rolled back. The serialization token controls the commencement of other processes of the computer system during the time that it is in force. The serialization is carried out by storing an abstract representation of the process to be serialized in storage which is accessible by all the programs and computers where the serialization applies.

Abstract: The invention relates to tracing the execution path of a computer program comprising at least one module including a plurality of instructions. At least one of these instructions is a branch instruction. Each branch instruction is identified and evaluated to be one of true and false. An evaluation of true results in a unique identifier being pushed into a predefined area of storage. This unique identifier is associated with the instructions executed as a result of an evaluation of true.

Abstract: Provided are a method and apparatus for providing serialization support for computer systems and computer system resources, in particular for application programs which require sequencing and/or consistency of data. The computer system resource includes serialized processes with units of work. A serialization token is provided at the start of a serialized process including at least one unit of work. The serialization token remains in force until the or all of the units of work of the process have been committed or rolled back. The serialization token controls the commencement of other processes of the computer system during the time that it is in force. The serialization is carried out by storing an abstract representation of the process to be serialized in storage which is accessible by all the programs and computers where the serialization applies.

Abstract: Provided are methods, data communication apparatus and computer programs for managing communications between a remote communication manager and a set of communications managers in an associated group. The group of communication managers have shared access to resources which enable any communication manager in the group to recover from failures experienced by another communication manager in the group. In particular, recovery of failed inbound and outbound channels is achieved with the advantage of improved availability of data transmissions. Preferably, the recovery uses synchronization information to ensure that data is recovered to a consistent state to that channel recovery is achieved without loss of data integrity.

Abstract: A method and apparatus for communicating message data between a plurality of subsystems (201, 202, 301, 302, 303, 404, 406, 408) in the form of distributed resource managers. The subsystems are coupled together through a coupling means (206, 306, 410) with a shared memory with at least one shared queue (308, 414) in the shared memory. Access to the shared queue (308, 414) is available from each of the coupled subsystems and message data can be communicated between the subsystems via the shared queue (308, 414). Each subsystem has a long running process (304) checking the shared queue for messages for that subsystem.

Abstract: A method and circuit for providing a reference voltage to a charge balance circuit. The method includes transferring charge corresponding to VBE and charge corresponding to &Dgr;VBE to a summing node of the charge balance circuit, where VBE is a voltage produced across a p-n junction and where &Dgr;VBE is a difference between two VBE voltages. With such method, instead of forming a bandgap reference circuit which produces a bandgap reference voltage and applying such voltage to the reference sampling and charge transfer circuit, charge corresponding to VBE and charge corresponding to &Dgr;VBE are transferred to the input summing node of the modulator in correct proportion and with a polarity corresponding to the modulator output.

Abstract: An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.

Abstract: A method, and apparatus, for calibrating a delta sigma modulator. The delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. During the calibration mode, a feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle and an input signal section samples a calibration signal and transfers packets of charge corresponding to a portion of the calibration signal to the integrating capacitor in each modulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thus reducing idle-tones.