Abstract: Opto-electronic packages and methods for making opto-electronic packages are disclosed, including a method comprising forming an opto-electronic circuit on a first surface of a substrate of a lower package assembly, the first surface of the substrate having a first bonding pattern configured to provide a hermetic seal, the first bonding pattern extending around the opto-electronic circuit; positioning a bottom of a ring frame onto the first bonding pattern so as to surround the opto-electronic circuit with the ring frame; hermetically sealing a bottom of the ring frame to the first bonding pattern of the first surface of the substrate of the lower package assembly subsequent to the formation of the opto-electronic circuit on the first surface of the substrate; and hermetically sealing a top of the ring frame to form a hermetically sealed opto-electronic package.

Abstract: Opto-electronic packages and methods for making opto-electronic packages are disclosed, including a method comprising forming an opto-electronic circuit on a first surface of a substrate of a lower package assembly, the first surface of the substrate having a first bonding pattern configured to provide a hermetic seal, the first bonding pattern extending around the opto-electronic circuit; positioning a bottom of a ring frame onto the first bonding pattern so as to surround the opto-electronic circuit with the ring frame; hermetically sealing a bottom of the ring frame to the first bonding pattern of the first surface of the substrate of the lower package assembly subsequent to the formation of the opto-electronic circuit on the first surface of the substrate; and hermetically sealing a top of the ring frame to form a hermetically sealed opto-electronic package.

Abstract: An optical transceiver package comprising a transceiver module, a digital signal processor (DSP), a substrate supporting the transceiver module and the DSP, and a barrier to mechanically protect and thermally insulate the transceiver module. The substrate comprises a material having a coefficient of thermal expansion (CTE) of 2.3-14 ppm/° C. and the barrier comprises a material having a CTE of 3.5-14 ppm/° C.

Abstract: Consistent with the present disclosure, a photonic integrated circuit (PIC) is provided that has 2 N channels (N being an integer). The PIC is optically coupled to N optical fibers, such that each of N polarization multiplexed optical signals are transmitted over a respective one of the N optical fibers. In another example, each of the N optical fibers supply a respective one of N polarization multiplexed optical signals to the PIC for coherent detection and processing. A multiplexer and demultiplexer may be omitted from the PIC, such that the optical signals are not combined on the PIC. As a result, the transmitted and received optical signals incur less loss and amplified spontaneous emission (ASE) noise. In addition, optical taps may be more readily employed on the PIC to measure outputs of the lasers, such as widely tunable lasers (WTLs), without crossing waveguides.

Abstract: Consistent with the present disclosure, a photonic integrated circuit (PIC) is provided that has 2 N channels (N being an integer). The PIC is optically coupled to N optical fibers, such that each of N polarization multiplexed optical signals are transmitted over a respective one of the N optical fibers. In another example, each of the N optical fibers supply a respective one of N polarization multiplexed optical signals to the PIC for coherent detection and processing. A multiplexer and demultiplexer may be omitted from the PIC, such that the optical signals are not combined on the PIC. As a result, the transmitted and received optical signals incur less loss and amplified spontaneous emission (ASE) noise. In addition, optical taps may be more readily employed on the PIC to measure outputs of the lasers, such as widely tunable lasers (WTLs), without crossing waveguides.

Abstract: Consistent with the present disclosure, a photonic integrated circuit (PIC) is provided that has 2 N channels (N being an integer). The PIC is optically coupled to N optical fibers, such that each of N polarization multiplexed optical signals are transmitted over a respective one of the N optical fibers. In another example, each of the N optical fibers supply a respective one of N polarization multiplexed optical signals to the PIC for coherent detection and processing. A multiplexer and demultiplexer may be omitted from the PIC, such that the optical signals are not combined on the PIC. As a result, the transmitted and received optical signals incur less loss and amplified spontaneous emission (ASE) noise. In addition, optical taps may be more readily employed on the PIC to measure outputs of the lasers, such as widely tunable lasers (WTLs), without crossing waveguides. In addition, wavelength locker (WLL) circuitry may be provided on the PIC.

Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Abstract: A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are removed to thereby expose the fill material. At least portions of the exposed fill material are removed to form a back-side through-substrate via opening that traverses an entire thickness of the substrate. The back-side through-substrate via opening is filled with an electrically conductive material.

Abstract: A method of manufacturing an integrated circuit package. The method comprises providing a carrier substrate having a planar surface. The method comprises placing a plurality of semiconductor device dies active-side down at laterally spaced-apart locations on the planar surface. The method comprises covering the semiconductor device dies with a mold compound to define laterally spaced-apart mold sub-arrays on the planar surface. The method comprises curing the laterally spaced-apart mold sub-arrays, wherein the semiconductor device dies are retained at substantially the same laterally spaced-apart locations on the planar surface after the curing.

Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Abstract: An electronic device includes first and second electronic device dice. The first electronic device die is embedded within a resin layer. A dielectric layer is located over the device die and the resin layer. First interconnects within the dielectric layer connect a first subset of electrical contacts on the first electronic device to corresponding terminals at a surface of the dielectric that are located over the first electronic device. Second interconnects within the dielectric layer connect a second subset of electrical contacts on the first electronic device to corresponding bump pads at a surface of the dielectric that are located over the resin layer.

Abstract: A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.

Abstract: A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.

Abstract: A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are removed to thereby expose the fill material. At least portions of the exposed fill material are removed to form a back-side through-substrate via opening that traverses an entire thickness of the substrate. The back-side through-substrate via opening is filled with an electrically conductive material.

Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Abstract: An electronic device includes first and second electronic device dice. The first electronic device die is embedded within a resin layer. A dielectric layer is located over the device die and the resin layer. First interconnects within the dielectric layer connect a first subset of electrical contacts on the first electronic device to corresponding terminals at a surface of the dielectric that are located over the first electronic device. Second interconnects within the dielectric layer connect a second subset of electrical contacts on the first electronic device to corresponding bump pads at a surface of the dielectric that are located over the resin layer.

Abstract: A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.

Abstract: An electronics package 100 comprising a substrate 105 having a planar surface 107, a memory die 110 and a logic die 120. Memory circuit components 112 interconnected to memory die contacts 114 located on an outer surface 116 of a face 118 of the memory die. Logic circuit components 122 interconnected to logic die contacts 124 located on an outer surface 126 of a face 128 of the logic die. Memory die contacts and the logic die contacts are interconnected such that the face of the memory die opposes the face of the logic die. A plurality of bonds 130 interconnect input-output contacts 132 on the planar surface of the substrate, to external die contacts 135 on one of the face of the logic die or the face of the memory die. One face opposes the planar surface, the other face is not directly connected to the interconnect input-output contacts.

Abstract: An integrated circuit package comprising an integrated circuit that includes transistors coupled to copper interconnect structures. The integrated circuit package also comprises copper pads located on the integrated circuit and directly contacting uppermost ones of the copper interconnect structures. Each of copper pads has a thickness of at least about 2 microns. The integrated circuit package further comprises copper wires pressure-welded directly to the copper pads.