Abstract: The specification describes a surface mount method for the manufacture of high device density circuit boards. The stand-off space of the components on the board can be enlarged significantly by selectively omitting, or selectively removing, the soldermask underneath the component package. This improves access of the cleaning fluid to the underside of the component during the cleaning operation.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: It has been found that composition containing copper, tin, and silver prevents tin whisker formation on an electronic structure while allowing solders to wet such structures during soldering processes. It has further been found that conventional techniques, such as electrolytic plating, electroless plating, wet dipping and vapor deposition, for forming such materials have undesirable limitations and/or characteristics. However, by forming a Ag/Sn precursor on a copper containing electronic structure and inducing a self-limiting reaction between the precursor and the copper of the structure, the advantageous Ag/Sn/Cu material is formed without the undesirable limitations and characteristics associated with conventional techniques.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: Device packages often include walls build on a heat sink that surrounds a device die that thermally interacts with the heat sink. Use of raised or depressed feature on said heat sink that contacts the walls improves the cohesiveness of the package. By appropriately positioning these features contaminant infusion into the package is improved without degrading cohesiveness.

Abstract: Devices such as amplifiers are built on a heat sink having a perimeter wall surrounding active electronic devices. Surprisingly formation of wire bonds to such devices tends to be degraded if they have an aspect ratio greater than 2:1. This problem is overcome by forming wire bonds before such walls have a height of 30 mils and after bond formation extending the walls to their final height.

Abstract: The specification describes a plastic cavity package for semiconductor devices that provides additional mechanical integrity for leads that extend from the plastic housing. Portions of the leads that are within the plastic housing are provided with cutouts. When the plastic housing is formed, or when the cavity is filled with polymer, plastic material fills the cutout, and joins to the mass of plastic on either side of the cutout, thus forming a continuous integral mass of plastic. The end result is that the plastic in the cutout, coupled to the main plastic mass, and to the rigid package sidewall, forms an effective anchor against pulling and bending forces the leads may encounter in manufacture or use.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage-base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: The specification describes a technique for die bonding that is tailored to air cavity plastic packages for high power devices. The die bonding method is simple and effective, and eliminates the step of placement of solder preforms in the die bonding operation. According to the invention the die that are to be attached are pre-coated with AuSn solder. A multifunctional bonding layer is applied between the silicon die and the AuSn bonding layer. The multifunctional bonding layer comprises a multi-layer structure including Ti/Pt/Au. The chip support member comprises copper or a copper alloy. The chip support member may also be pre-coated with a bonding layer. The pre-coated die is soldered to the chip support member.

Abstract: The electrical and mechanical properties of structures such as lead frames and other electrical/electronic devices containing, during processing, copper/tin interfaces are improved by introduction of nickel to such interface. Typically, a weight percentage of nickel to tin in the range 1 to 12 weight percent yields upon melting of the tin, an intermetallic compound with essentially no occluded, unbound tin. Thus undesirable anomalous structures such as tin needles and substantially non-planar interface compositions are avoided. Advantageously a nickel/tin/copper intermetallic interface that is substantially planar is formed in the substantial absence of needle-like tin structures.

Abstract: An encapsulating compound includes an organic polymeric carrier material and a dielectric filler material added to the polymeric carrier material. The dielectric filler material has a dielectric constant associated therewith which is less than a dielectric constant of the polymeric carrier material. The dielectric filler material is interspersed with the polymeric carrier material such that a dielectric constant of the encapsulating compound is less than the dielectric constant of the polymeric carrier material alone.

Abstract: The specification describes a surface mount method for the manufacture of high device density circuit boards. The stand-off space of the components on the board can be enlarged significantly by selectively omitting, or selectively removing, the soldermask underneath the component package. This improves access of the cleaning fluid to the underside of the component during the cleaning operation.

Abstract: Power transistor devices and techniques for reducing bowing in such devices are provided. In one aspect, a power transistor device is provided. The power transistor device comprises a substrate, a device film formed on the substrate and an adhesion layer formed on a side of the substrate opposite the device film, wherein at least a portion of the adhesion layer is at least partially segmented. The power transistor device thereby exhibits a reduced amount of bowing relative to an amount of bowing expected without the segmenting of the adhesion layer. The power transistor device may be part of an integrated circuit.

Abstract: A process includes annealing one or more plated conductive leads at a predetermined temperature. The one or more plated conductive leads are plated with one or more layers, where each layer comprises a material. The predetermined temperature is greater than or equal to approximately a melting point of one of the materials. The annealing can reduce growth formations, such as whiskers, on the one or more conductive leads. Lead frames and other devices having plated conductive leads may be subjected to the process, and the resultant plated conductive leads will have fewer growth formations than plated conductive leads not subjected to the process. The plated conductive leads may be trimmed and formed prior to or after the anneal.

Abstract: Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.

Abstract: A structure for holding an optical subassembly such as a laser and which minimizes the tilt of the optical subassembly. Pads are placed between the optical subassembly and the housing forming grooves along the inside of the housing and between the pads. The solder for mounting the subassembly to the housing is placed in the grooves. The volume of the solder is chosen so that it does not overflow the grooves. But the solder can be constructed so that its height is greater than the height of the grooves. The optical subassembly is placed against the solder with a downward force and heat is applied to the bottom of the base to melt the solder.