Patents by Inventor John P. Bettencourt
John P. Bettencourt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230299768Abstract: A common gate input circuit for III/V D-mode Buffered FET Logic (BFL) maximizes the dynamic range to drive a level shift section to set the proper voltage levels to switch the BFL and allows for decoupling of the switch point from the dynamic range. A common gate switching section includes a D-mode FET (FET1) configured as a load and a D-mode FET (FET2) configured as a common gate connected in series between high and low supplies Vdd and Vee1 (typically ground potential). The gate electrode of FET2 is coupled to Vee1 and the source electrode of FET2 is driven by the external digital signals. This eliminates the additional supply Vss, thus maximizing the dynamic range of the section to switch between Vdd and Vee1 and decouples the dynamic range from the switch point. An input level shift section may shift the Data In to the source electrode of FET2 to shift the switch point and to present a high input impedance.Type: ApplicationFiled: March 17, 2022Publication date: September 21, 2023Inventor: John P. Bettencourt
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Publication number: 20230208364Abstract: Methods and apparatus for an amplifier including first and second transistors coupled in a stacked configuration with first and second current mirrors to provide respective bias signals to the amplifier transistors. A reference transistor is coupled to the first and second current mirrors for referencing the bias signals together.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Applicant: Raytheon CompanyInventors: John P. Bettencourt, Valery S. Kaper, Steven M. Lardizabal
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Patent number: 11682721Abstract: A high electron mobility transistor (HEMT) includes a substrate; a source on the substrate; a drain on the substrate spaced from the source; and a gate between the source and the drain, wherein the gate has a stem contacting the substrate, the stem having a source side surface and a drain side surface, wherein a source side angle is defined between the source side surface and an upper planar surface of the substrate and a drain side angle is defined between the drain side surface and the upper planar surface of the substrate, and wherein the source side angle and the drain side angle are asymmetric. Methods for making the HEMT are also disclosed.Type: GrantFiled: January 20, 2021Date of Patent: June 20, 2023Assignee: Raytheon CompanyInventors: Matthew Thomas Dejarld, John P. Bettencourt, Adam Lyle Moldawer, Kenneth A. Wilson
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Patent number: 11476154Abstract: A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.Type: GrantFiled: September 26, 2019Date of Patent: October 18, 2022Assignee: Raytheon CompanyInventors: Jeffrey R. LaRoche, John P. Bettencourt, Paul J. Duval, Kelly P. Ip
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Publication number: 20220231154Abstract: A high electron mobility transistor (HEMT) includes a substrate; a source on the substrate; a drain on the substrate spaced from the source; and a gate between the source and the drain, wherein the gate has a stem contacting the substrate, the stem having a source side surface and a drain side surface, wherein a source side angle is defined between the source side surface and an upper planar surface of the substrate and a drain side angle is defined between the drain side surface and the upper planar surface of the substrate, and wherein the source side angle and the drain side angle are asymmetric. Methods for making the HEMT are also disclosed.Type: ApplicationFiled: January 20, 2021Publication date: July 21, 2022Applicant: Raytheon CompanyInventors: Matthew Thomas Dejarld, John P. Bettencourt, Adam Lyle Moldawer, Kenneth A. Wilson
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Patent number: 11145735Abstract: Forming an ohmic contact sealing layer disposed at an intersection between a sidewall of an ohmic contact and a surface of a semiconductor; forming an ohmic contact sealing layer on the intersection between a sidewall of the ohmic contact and the surface of the semiconductor; and subjecting the semiconductor with the ohmic contact to a chemical etchant.Type: GrantFiled: October 11, 2019Date of Patent: October 12, 2021Assignee: RAYTHEON COMPANYInventors: Paul J. Duval, John P. Bettencourt, James W. McClymonds, Paul M. Alcorn, Philip C. Balas, II, Michael S. Davis
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Publication number: 20210111263Abstract: Forming an ohmic contact sealing layer disposed at an intersection between a sidewall of an ohmic contact and a surface of a semiconductor; forming an ohmic contact sealing layer on the intersection between a sidewall of the ohmic contact and the surface of the semiconductor; and subjecting the semiconductor with the ohmic contact to a chemical etchant.Type: ApplicationFiled: October 11, 2019Publication date: April 15, 2021Applicant: Raytheon CompanyInventors: Paul J. Duval, John P. Bettencourt, James W. McClymonds, Paul M. Alcorn, Philip C. Balas, II, Michael S. Davis
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Publication number: 20210098285Abstract: A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Applicant: Raytheon CompanyInventors: Jeffrey R. LaRoche, John P. Bettencourt, Paul J. Duval, Kelly P. Ip
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Patent number: 10593665Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.Type: GrantFiled: September 19, 2018Date of Patent: March 17, 2020Assignee: Raytheon CompanyInventors: John P. Bettencourt, Raghuveer Mallavarpu
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Patent number: 10447208Abstract: A circuit having (A) a transistor; (B) a bias circuit for providing setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit; and (C) a bias current level controller, comprising: (i) a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and (ii) current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and a corresponding one of the plurality of switches, the current source circuit combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET, the combined current providing the reference current fed to the bias circuit.Type: GrantFiled: December 15, 2017Date of Patent: October 15, 2019Assignee: Raytheon CompanyInventors: John P. Bettencourt, Valery S. Kaper, Steven M. Lardizabal
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Publication number: 20190190456Abstract: A circuit having (A) a transistor, (B) a bias circuit for providing setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit; and (C) a bias current level controller, comprising: (i) a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and (ii) current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and a corresponding one of the plurality of switches, the current source circuit combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET, the combined current providing the reference current fed to the bias circuit.Type: ApplicationFiled: December 15, 2017Publication date: June 20, 2019Applicant: Raytheon CompanyInventors: John P. Bettencourt, Valery S. Kaper, Steven M. Lardizabal
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Patent number: 10277176Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.Type: GrantFiled: February 9, 2018Date of Patent: April 30, 2019Assignee: Raytheon CompanyInventors: John P. Bettencourt, Alan J. Bielunis, Istvan Rodriguez, Zhaoyang C. Wang
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Publication number: 20190019790Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.Type: ApplicationFiled: September 19, 2018Publication date: January 17, 2019Applicant: Raytheon CompanyInventors: John P. Bettencourt, Raghuveer Mallavarpu
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Patent number: 10103137Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.Type: GrantFiled: March 24, 2017Date of Patent: October 16, 2018Assignee: Raytheon CompanyInventors: John P. Bettencourt, Raghuveer Mallavarpu
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Publication number: 20180167041Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.Type: ApplicationFiled: February 9, 2018Publication date: June 14, 2018Applicant: Raytheon CompanyInventors: John P. Bettencourt, Alan J. Bielunis, Istvan Rodriguez, Zhaoyang C. Wang
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Patent number: 9960740Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.Type: GrantFiled: June 7, 2016Date of Patent: May 1, 2018Assignee: Raytheon CompanyInventors: John P. Bettencourt, Alan J. Bielunis, Istvan Rodriguez, Zhaoyang C. Wang
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Patent number: 9799645Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.Type: GrantFiled: November 20, 2015Date of Patent: October 24, 2017Assignee: Raytheon CompanyInventors: John P. Bettencourt, Raghuveer Mallavarpu
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Patent number: 9793859Abstract: An amplifier system having: an amplifier having a linear operating region where an output signal produced by the amplifier at the output terminal has a power level increasing proportionally with the increasing input signal power level up to a compression region of the amplifier where the output power is inhibited from increasing with increasing input signal power; and a DC current limiting circuit, coupled between a DC power supply and the amplifier, to: supply DC current from the DC power supply that is equal to quiescent current to the amplifier from the DC power supply when the amplifier operates in the linear region; enable the amplifier to draw increasing DC current from the DC power supply above the quiescent current with increasing input signal power until the output signal power reaches the desired compression point level which is lower than that of a stand-alone amplifier without the DC current limiting circuit; and, then limits the current drawn by the amplifier from the DC power supply.Type: GrantFiled: September 27, 2016Date of Patent: October 17, 2017Assignee: Raytheon CompanyInventors: Valery S. Kaper, John P. Bettencourt
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Publication number: 20170200713Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.Type: ApplicationFiled: March 24, 2017Publication date: July 13, 2017Applicant: Raytheon CompanyInventors: John P. Bettencourt, Raghuveer Mallavarpu
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Publication number: 20170148783Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.Type: ApplicationFiled: November 20, 2015Publication date: May 25, 2017Applicant: Raytheon CompanyInventors: John P. Bettencourt, Raghuveer Mallavarpu