Patents by Inventor John P. Dubuque
John P. Dubuque has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10970448Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.Type: GrantFiled: July 18, 2019Date of Patent: April 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett, Lansing D. Pickup, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 10489540Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.Type: GrantFiled: November 13, 2017Date of Patent: November 26, 2019Assignee: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladimir Zolotov
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Publication number: 20190340323Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.Type: ApplicationFiled: July 18, 2019Publication date: November 7, 2019Inventors: Brian M. DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Jeffrey G. HEMMETT, Lansing D. PICKUP, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Patent number: 10394982Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.Type: GrantFiled: February 26, 2014Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett, Lansing D. Pickup, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Publication number: 20180096089Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.Type: ApplicationFiled: November 13, 2017Publication date: April 5, 2018Inventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladimir Zolotov
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Patent number: 9858368Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.Type: GrantFiled: July 13, 2011Date of Patent: January 2, 2018Assignee: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladmimir Zolotov
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Publication number: 20160378903Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: Nathan Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 9519747Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.Type: GrantFiled: June 26, 2015Date of Patent: December 13, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Nathan Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 9378328Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: GrantFiled: November 25, 2014Date of Patent: June 28, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 9348962Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.Type: GrantFiled: August 19, 2014Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 9171124Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.Type: GrantFiled: December 23, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Publication number: 20150242554Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.Type: ApplicationFiled: February 26, 2014Publication date: August 27, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian M. DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Jeffrey G. HEMMETT, Lansing D. PICKUP, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Publication number: 20150082260Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: ApplicationFiled: November 25, 2014Publication date: March 19, 2015Inventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Peter A. HABITZ, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Patent number: 8949765Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: GrantFiled: December 23, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Publication number: 20140359547Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.Type: ApplicationFiled: August 19, 2014Publication date: December 4, 2014Inventors: Nathan BUCK, Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Publication number: 20140298280Abstract: Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis.Type: ApplicationFiled: April 2, 2013Publication date: October 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, David J. HATHAWAY, Jeffrey G. HEMMETT, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Patent number: 8850378Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.Type: GrantFiled: October 31, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 8839167Abstract: Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis.Type: GrantFiled: April 2, 2013Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 8806402Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.Type: GrantFiled: October 31, 2012Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 8769452Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.Type: GrantFiled: October 31, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Nathan Buck, Brian Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov