Patents by Inventor John P. Lesso
John P. Lesso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11653855Abstract: A method of cough detection in a headset, the method comprising: receiving a first signal from an external transducer of the headset; receiving a second signal from an in-ear transducer of the headset; and detecting a cough of a user of the headset based on the first and second signals.Type: GrantFiled: December 3, 2021Date of Patent: May 23, 2023Assignee: Cirrus Logic, Inc.Inventors: John P. Lesso, Yanto Suryono, Toru Ido
-
Publication number: 20230155581Abstract: This application relates to methods and apparatus for controlling slew-rate of components for outputting an analogue output signal. Described is a signal processing circuit having a forward signal path for receiving an input signal and outputting an analogue output signal. The signal processing circuit has a first component located in said forward signal path for outputting the analogue output signal. A predictor is configured to predict a required slew-rate for the first component based on the input signal and a controller is configured to controllably vary an output slew-rate limit of the first component based on the prediction of required slew-rate.Type: ApplicationFiled: September 7, 2022Publication date: May 18, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Peter J. TONGE, John P. LESSO
-
Patent number: 11652405Abstract: A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.Type: GrantFiled: June 3, 2021Date of Patent: May 16, 2023Assignee: Cirrus Logic, Inc.Inventors: John P. Lesso, John L. Pennock, Peter J. Frith
-
Patent number: 11652406Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes, two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/?3VV, +/?VV/5 or +/?VV/6.Type: GrantFiled: October 5, 2021Date of Patent: May 16, 2023Assignee: Cirrus Logic, Inc.Inventors: John P. Lesso, Peter J. Frith, John L. Pennock
-
Patent number: 11646708Abstract: The present disclosure relates to circuitry for driving a piezoelectric transducer. The circuitry comprises amplifier circuitry configured to receive a drive signal and to output an output signal, based on the drive signal, to the piezoelectric transducer, a variable capacitor configured to be coupled in series with the piezoelectric transducer, and control circuitry. The control circuitry is configured to control a capacitance of the variable capacitor to compensate for hysteresis in the piezoelectric transducer and to control a gain of the amplifier circuitry to compensate for signal attenuation caused by the variable capacitor.Type: GrantFiled: December 7, 2020Date of Patent: May 9, 2023Assignee: Cirrus Logic, Inc.Inventors: John P. Lesso, Toru Ido
-
Publication number: 20230134523Abstract: Circuitry for measuring a characteristic of an electrochemical cell, the circuitry comprising: a comparator having a first comparator input, a second comparator input and a comparator output; a feedback path between the comparator output and the second comparator input configured to provide a feedback signal to the second comparator input; and a loop filter configured to apply filtering to the feedback path to generate the feedback signal, wherein the loop filter comprises the electrochemical cell.Type: ApplicationFiled: November 4, 2021Publication date: May 4, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventor: John P. LESSO
-
Patent number: 11627401Abstract: A method for on ear detection for a headphone, the method comprising: receiving a first microphone signal derived from a first microphone of the headphone and determining, from the first microphone signal, a first resonance frequency associated with an acoustic port of the first microphone, the first resonance frequency dependent on a first temperature at the first microphone; receiving a second microphone signal derived from a second microphone of the headphone and determining, from the second microphone signal, a second resonance frequency associated with an acoustic port of the second microphone, the second resonance frequency dependent on a second temperature at the second microphone.Type: GrantFiled: July 23, 2021Date of Patent: April 11, 2023Assignee: Cirrus Logic, Inc.Inventor: John P. Lesso
-
Patent number: 11627414Abstract: A microphone system, comprises a first transducer, for generating a first acoustic signal, and a second transducer, for generating a second acoustic signal. A high-pass filter receives the first signal and generates a first filtered signal, and a low-pass filter receives the second signal and generates a second filtered signal. An adder forms an output signal of the microphone system as a sum of the first filtered signal and the second filtered signal.Type: GrantFiled: March 31, 2022Date of Patent: April 11, 2023Assignee: Cirrus Logic, Inc.Inventors: John P. Lesso, Thomas I. Harvey
-
Publication number: 20230107777Abstract: An apparatus, comprising: an audio input for receiving an input audio signal; an tuning input for receiving a tuning signal; a filter chain comprising a plurality of filters for filtering the audio signal to produce a filtered input audio signal, the filter chain comprising: a first filter module operating at a first sampling rate; and a second filter module operating at a second sampling rate greater than the first sampling rate, wherein a phase response of the first filter module is dependent on the tuning input and wherein a magnitude response of the first filter module is substantially independent of the tuning input.Type: ApplicationFiled: May 20, 2022Publication date: April 6, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventor: John P. LESSO
-
Patent number: 11601760Abstract: A system for driving a transducer having a plurality of coils, the system comprising: a modulator for outputting a digital output signal representative of a received analogue input signal at a modulator output; a clock controlled delay element for applying a delay to the digital output signal to generate a first delayed signal at a delay element output; wherein the modulator output is couplable to a first coil of the plurality of the coils of the transducer and the delay element output is couplable to a second coil of the plurality of coils of the transducer.Type: GrantFiled: January 19, 2022Date of Patent: March 7, 2023Assignee: Cirrus Logic, Inc.Inventor: John P. Lesso
-
Patent number: 11600280Abstract: An analogue-to-digital converter (ADC), comprising: an adaptive whitening filter configured to filter an analogue input signal and output a whitened analogue input signal; a first converter configured to receive said whitened analogue input signal and output a whitened digital signal; a controller configured to adapt the whitening filter based on the received analogue input signal.Type: GrantFiled: September 29, 2020Date of Patent: March 7, 2023Assignee: Cirrus Logic, Inc.Inventor: John P. Lesso
-
Publication number: 20230061184Abstract: Circuitry for measuring a characteristic of an electrochemical cell, the circuitry comprising: a comparator having a first comparator input, a second comparator input and a comparator output; a feedback path between the comparator output and the second comparator input configured to provide a feedback signal to the second comparator input; and a loop filter configured to apply filtering to the feedback path to generate the feedback signal, wherein the loop filter comprises the electrochemical cell.Type: ApplicationFiled: September 1, 2021Publication date: March 2, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: John P. LESSO, Toru IDO
-
Publication number: 20230059646Abstract: Balancing circuitry for balancing a set of N cells in a battery, the balancing circuitry comprising: a switch network configured to be coupled to the cells; and a set of capacitors coupled in parallel between the switch network and a common node, wherein the switch network is controllable such that: during a first phase of operation of the balancing circuitry the set of capacitors is coupled to a first subset comprising N?1 adjacent cells of the set of N cells; and during a second phase of operation the set of capacitors is coupled to a second subset comprising N?1 adjacent cells of the set of N cells, wherein the second subset is different from the first subset, and wherein, in use of the balancing circuitry, the common node is coupled intermittently, periodically or permanently to a reference voltage.Type: ApplicationFiled: August 5, 2022Publication date: February 23, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: John P. LESSO, Toru IDO
-
Publication number: 20230059155Abstract: Circuitry for balancing cells in a battery pack, the circuitry comprising: cell balancing circuitry configured to transfer energy between cells of the battery pack in synchronisation with a clock signal; and control circuitry configured to control a parameter of the clock signal based on a monitored parameter or information associated with the battery pack.Type: ApplicationFiled: August 3, 2022Publication date: February 23, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: John P. LESSO, Toru IDO
-
Publication number: 20230053745Abstract: Balancing circuitry for balancing cells in first and second modules of a battery pack, wherein the first module comprises a first plurality of cells and the second module comprises a second plurality of cells, the balancing circuitry comprising: first cell balancing circuitry operative to balance the first plurality of cells of the first module; and second cell balancing circuitry operative to balance the second plurality of cells of the second module, wherein the second cell balancing circuitry is further operative to balance at least one cell of the first plurality of cells of the first module with at least one cell of the second plurality of cells of the second module.Type: ApplicationFiled: August 4, 2022Publication date: February 23, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: John P. LESSO, Toru IDO, Anthony S. DOY
-
Patent number: 11588452Abstract: Class D amplifier circuitry comprising: modulator circuitry; and output stage circuitry, wherein the modulator circuitry is configured to: receive an input signal and first and second carrier signals, wherein the second carrier signal is offset in amplitude with respect to the first carrier signal; generate first and second modulated output signals, each of the first and second modulated output signals being based on the input signal and the first and second carrier signals; and generate a plurality of control signals for the output stage circuitry per signal period of the modulated output signals, wherein the plurality of control signals are based on the first and second modulated output signals, and wherein at least one of the plurality of control signals per signal period comprises a signal level transition.Type: GrantFiled: February 26, 2021Date of Patent: February 21, 2023Assignee: Cirrus Logic, Inc.Inventors: John P. Lesso, David P. Singleton
-
Publication number: 20230046369Abstract: The present disclosure relates to circuitry for performing a multiply-accumulate (MAC) operation. The circuitry comprises a first multiplexer having a plurality of inputs for receiving a plurality of unary-coded input signals representing operands of the MAC operation and an output for outputting a multiplexer output signal representing a result of the MAC operation and a first vector quantizer configured to receive a plurality of weighting signals, each representing a proportion of a computation time period for which a respective one of the unary-coded input signals should be selected by the multiplexer and to output a first selector signal to the multiplexer to cause the multiplexer to select each of the input signals in accordance with the plurality of weighting signals.Type: ApplicationFiled: July 29, 2021Publication date: February 16, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: John P. LESSO, John L. MELANSON
-
Publication number: 20230030111Abstract: The present disclosure relates to switching drivers for driving a transducer. A switching driver (202) has supply nodes for receiving supply voltages (VSH, VSL) defining at least one input voltage and an output node (104). A controller (205) controls operation of the first switching driver to generate a drive signal for the transducer at the output node (104), based on an input signal (Sin). A first capacitor (201a) is connected between first and second capacitor nodes (104, 204a) and a second capacitor (201b) is connected between the second capacitor node (204a) and a third capacitor node (204b). A network of switches (203) selectively connects any of the driver output node, the second capacitor node and the third capacitor node to either of a respective pair of said supply nodes, with the first capacitor node connected to the first driver output node.Type: ApplicationFiled: June 8, 2022Publication date: February 2, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: John P. LESSO, John L. MELANSON
-
Publication number: 20230018755Abstract: A method of equalising an audio signal derived from a microphone, the method comprising: receiving the audio signal; applying an order-statistic filter to the audio signal in the frequency domain to generate a statistically filtered audio signal; equalising the received audio signal based on the statistically filtered audio signal to generate an equalised audio signal.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: John P. LESSO, Craig Alexander ANDERSON
-
Patent number: 11552609Abstract: The present disclosure relates to amplifier circuitry (300) that includes a linear amplifier stage (110) that receives an input signal and outputs a first drive signal to an output node (302) and a switching amplifier stage (130) operable to output a second drive signal to the output node (302). A controller (340) is selectively operable in a first dual-amplifier mode, in which switching of the switching amplifier stage is controlled based on a current of the first drive signal, such that the current of the first drive signal does not exceed a first current threshold magnitude; and at least one other mode, in which the controller controls the switching amplifier stage such that the current of the first drive signal may exceed the first current threshold magnitude. The controller (340) selectively controls the mode of operation based on an indication (SSL) of signal level of the output signal.Type: GrantFiled: March 2, 2021Date of Patent: January 10, 2023Assignee: Cirrus Logic, Inc.Inventor: John P. Lesso