Abstract: A silicon-on-insulator (SOI) photodiode optical monitoring method and system for color temperature control in solid state light systems. The method includes the steps of providing a plurality of SOI photodiodes, wherein each SOI photodiode includes a silicon substrate, a buried oxide layer formed on the silicon substrate, and a silicon layer formed on the buried oxide layer, and wherein the silicon layer of each SOI photodiode has a different thickness, determining a proportion of incident light passing through each SOI photodiode to the silicon substrate with respect to wavelength and the thickness of the silicon layer, and calculating color component intensities of the incident light based on the determined proportions.

Abstract: A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a voltage significantly less than the handler wafer (304) and drain, a condition under which prior art SOI devices may not properly operate.

Abstract: The present invention provides a semiconductor device of the SOI-LDMOS type in which the field plate is divided into a plurality of electrically isolated sub-field plates. At least two of the divided sub-field plates are connected to external circuits for reading their respective output voltages. By connecting a first external circuit and a second external circuit having specific components, one is configured for determining an instantaneous output voltage and the other is configured for determining a change in output voltage as a function of time. Power is disconnected from the semiconductor device if either the instantaneous voltage or the derivative of voltage over time exceeds an established value.

Abstract: A hybrid semiconductor device is presented in which one or more diode regions are integrated into a transistor region. In a preferred embodiment the transistor region is a continuous (self-terminating) SOI LDMOS device in which are integrated one or more diode portions. Within the diode portions, since there is only one PN junction, the mechanism for breakdown failure due to bipolar turn-on is nonexistent. The diode regions are formed such that they have a lower breakdown voltage than the transistor region, and thus any transient voltage (or current) induced breakdown is necessarily contained in the diode regions. In a preferred embodiment, the breakdown voltage of the diode portions is lowered by narrowing their field plate length relative to the transistor portion of the device. This allows the device to survive any such breakdown without being destroyed, resulting in a more rugged and more reliable device.

Abstract: A hybrid semiconductor device is presented in which one or more diode regions are integrated into a transistor region. In a preferred embodiment the transistor region is a continuous (self-terminating) SOI LDMOS device in which are integrated one or more diode portions. Within the diode portions, since there is only one PN junction, the mechanism for breakdown failure due to bipolar turn-on is nonexistent. The diode regions are formed such that they have a lower breakdown voltage than the transistor region, and thus any transient voltage (or current) induced breakdown is necessarily contained in the diode regions. In a preferred embodiment, the breakdown voltage of the diode portions is lowered by narrowing their field plate length relative to the transistor portion of the device. This allows the device to survive any such breakdown without being destroyed, resulting in a more rugged and more reliable device.

Abstract: The present invention provides a semiconductor device of the SOI-LDMOS type in which the field plate is divided into a plurality of electrically isolated sub-field plates. At least two of the divided sub-field plates are connected to external circuits for reading their respective output voltages. By connecting a first external circuit and a second external circuit having specific components, one is configured for determining an instantaneous output voltage and the other is configured for determining a change in output voltage as a function of time. Power is disconnected from the semiconductor device if either the instantaneous voltage or the derivative of voltage over time exceeds an established value.

Abstract: A lateral insulated gate bipolar PMOS device includes a semiconductor substrate, a buried insulating layer and a lateral PMOS transistor device in an SOI layer on the buried insulating layer having a source region of p-type conductivity. A lateral drift region of n-type conductivity is provided adjacent the body region, and a drain region of the p-type conductivity is provided laterally spaced from the body region by the drift region. An n-type conductivity drain region is formed of a shallow n-type contact surface region inserted into a p-inversion buffer. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.

Abstract: A lateral high voltage semiconductor device having a sense terminal and a method for sensing a drain voltage of the same are provided. Specifically, the present invention relates to a thin layer, high voltage, lateral silicon-on-insulator (SOI) device having a field plate terminal that is disconnected from a source terminal. By measuring voltage or current on the separate field plate terminal, the drain voltage of the device can be sensed. This sensing capability is a protection scheme against overstress voltage conditions.

Abstract: A lateral high voltage semiconductor device having a sense terminal and a method for sensing a drain voltage of the same are provided. Specifically, the present invention relates to a thin layer, high voltage, lateral silicon-on-insulator (SOI) device having a field plate terminal that is disconnected from a source terminal. By measuring voltage or current on the separate field plate terminal, the drain voltage of the device can be sensed. This sensing capability is a protection scheme against overstress voltage conditions.

Abstract: An improved method and structure for a transistor device with a lateral drift region and a conducting top field plate is presented. The method consists of decreasing the gate to drain capacitance by means of decreasing the portion of the field plate that is connected to the gate electrode, and hence the effective overlap of the gate with the drift region and drain. This results in decreased energy dissipation in switching the transistor, and more efficient operation. The rate of decrease of the gate to drain capacitance is even faster at higher drain voltages, inuring in significant energy efficiencies in high voltage applications.

Abstract: An improved method and structure for a transistor device with a lateral drift region and a conducting top field plate is presented. The method consists of decreasing the gate to drain capacitance by means of decreasing the portion of the field plate that is connected to the gate electrode, and hence the effective overlap of the gate with the drift region and drain. This results in decreased energy dissipation in switching the transistor, and more efficient operation. The rate of decrease of the gate to drain capacitance is even faster at higher drain voltages, inuring in significant energy efficiencies in high voltage applications.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a Lateral Insulated Gate Bipolar Transistor (LIGBT) device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first and a body contact region of the second conductivity type in the body region and connected to the source region. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region with an anode region of the second conductivity type in the drain region and connected to the drain contact region.

Abstract: Epitaxial layers of II-VI semiconductor compounds having low incidence of lattice defects such as stacking faults are produced by first depositing a fraction of a monolayer of the cation species of the compound, followed by depositing a thin layer of the compound by migration enhanced epitaxy (MEE). Growth of the remainder of the layer by MBE results in much lower defects than if the entire layer had been grown by MBE. Layers are useful in devices such as LEDs and injection lasers.

Abstract: Epitaxial layers of II-VI semiconductor compounds having low incidence of lattice defects such as stacking faults are produced by first depositing a fraction of a monolayer of the cation species of the compound, followed by depositing a thin layer of the compound by migration enhanced epitaxy (MEE). Growth of the remainder of the layer by MBE results in much lower defects than if the entire layer had been grown by MBE. Layers are useful in devices such as LEDs and injection lasers.

Abstract: A blue-green II/VI semiconductor injection laser utilizing a Zn.sub.1-u Cd.sub.u Se active layer (quantum well) having Zn.sub.1-x Mg.sub.x S.sub.y Se.sub.1-y cladding layers and ZnS.sub.z Se.sub.1-z guiding layers on a GaAs substrate. These devices are operable in a pulse mode at room temperature.