Patents by Inventor John R. Mick

John R. Mick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200104533
    Abstract: Systems, apparatuses, and methods are described for protecting the integrity of a playlist, and/or for determining whether a playlist has been altered. The playlist may comprise references to segments of multiple content types. The references may be obfuscated, and/or confirmation data may be used to detect playlist alteration.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 2, 2020
    Inventors: John R. Mick, SR., Sean E. Bowman, Cory Zachman, Christopher D. Brown, Mark Niebur
  • Patent number: 8069464
    Abstract: In one embodiment, a method comprises determining ad placement times for each of a plurality of associated streams. The method also comprises determining an ad selection request time for each of a plurality of ad selection requests based on a cumulative effect of any other ad selection requests occurring at substantially the same time as the determined ad selection time. Each of the plurality of ad selection requests corresponds to one of the plurality of ad placement times.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: November 29, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: John Pickens, John R. Mick, Jr.
  • Patent number: 7636300
    Abstract: Phone-based remote media system interaction is described. A content distribution system provides a telephone-based voice menu system that enables a caller to select a media system control command. The content distribution system then causes the media system control command to be executed in association with a remote media system associated with, or specified by, the caller.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: December 22, 2009
    Assignee: Microsoft Corporation
    Inventors: Samuel Thomas Scott, III, John R Mick, Jr.
  • Publication number: 20090031339
    Abstract: In one embodiment, a method comprises determining ad placement times for each of a plurality of associated streams. The method also comprises determining an ad selection request time for each of a plurality of ad selection requests based on a cumulative effect of any other ad selection requests occurring at substantially the same time as the determined ad selection time. Each of the plurality of ad selection requests corresponds to one of the plurality of ad placement times.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 29, 2009
    Inventors: John Pickens, John R. Mick, JR.
  • Publication number: 20090025026
    Abstract: In one embodiment, a method can include: (i) receiving a placement opportunity in an ad decision manager (ADM); (ii) sending a request to an ad decision server (ADS); (iii) receiving a conditional response from the ADS, wherein the conditional response includes one or more conditional ads; and (iv) selecting from among the one or more conditional ads.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 22, 2009
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: John R. Mick, JR., John Pickens
  • Patent number: 7260675
    Abstract: CAM-based search engines may be configured to support multiple databases within a CAM core. These databases may represent tables for different applications, which can be searched sequentially in response to a single indirect instruction that is loaded during a control cycle. The databases to be searched may be identified by a multi-database search instruction that is loaded during a single data cycle, which may overlap with the control cycle. In some cases, the databases may be searched using variations of a primary search key, so that it is unnecessary to repeatedly load the entire search key across a network interface for each search operation within a respective database. Instead, shorter replacement key segments may be loaded for each of a plurality of the search operations and these replacement key segments may be combined with one or more segments of the primary search key in the CAM core to define a desired search key for a respective search operation.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: August 21, 2007
    Assignee: Integrated Device Technology, Inc.
    Inventors: Harmeet Bhugra, Kenneth Branth, John R. Mick, Jr., Jakob Saxtorph
  • Patent number: 7194573
    Abstract: CAM-based search engine devices operate to reduce the occurrence of duplicate learned entries within a CAM database when processing search and learn (SNL) instructions. A search engine device may be configured to support processing of first and second immediately consecutive and equivalent SNL instructions as a first SNL instruction and a second search and search instruction, respectively. This processing is performed in order to block an addition of a duplicate learned entry within a database in the search engine device. The search engine device may also be configured to selectively block processing of the second SNL instruction as a second search and search instruction in response to detecting the database as full when the first SNL instruction is processed.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: March 20, 2007
    Assignee: Integrated Device Technology, Inc.
    Inventors: Jakob Saxtorph, John R. Mick, Jr., Harmeet Bhugra
  • Patent number: 7185172
    Abstract: An integrated circuit chip includes a search engine including a content addressable memory (CAM) configured to produce CAM indices responsive to search instructions provided to the search engine. The search engine further includes an index translation circuit operatively coupled to the CAM and configured to provide translation of the CAM indices to another memory space, such as from an absolute index space associated with the CAM to a memory space associated with a database within the CAM or to a memory space of a device external to the chip, such as a command source or external SRAM.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: February 27, 2007
    Assignee: Integrated Device Technology, Inc.
    Inventors: John R. Mick, Jr., Jakob Saxtorph, Harmeet Bhugra
  • Patent number: 7120733
    Abstract: Integrated search engine devices include a content addressable memory (CAM) core that is configured to support at least one database of searchable entries therein and a control circuit. The control circuit is configured to support reporting to a command host of data identifying entries that have been aged out of the at least one database and/or entries that have exceeded an activity-based aging threshold. The control circuit is further configured to support age reporting that is programmable on a per entry basis within the at least one database.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: October 10, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: John R. Mick, Jr, Harmeet Bhugra, Jakob Saxtorph
  • Patent number: 7120731
    Abstract: CAM-based search engines may be configured to support multiple databases within a CAM core. These databases may represent tables for different applications, which can be searched sequentially in response to a single indirect instruction that is loaded during a control cycle. The databases to be searched may be identified by a multi-database search instruction that is loaded during a single data cycle, which may overlap with the control cycle. In some cases, the databases may be searched using variations of a primary search key, so that it is unnecessary to repeatedly load the entire search key across a network interface for each search operation within a respective database. Instead, shorter replacement key segments may be loaded for each of a plurality of the search operations and these replacement key segments may be combined with one or more segments of the primary search key in the CAM core to define a desired search key for a respective search operation.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: October 10, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Harmeet Bhugra, Kenneth Branth, John R. Mick, Jr., Jakob Saxtorph
  • Patent number: 7082493
    Abstract: CAM-based search engines and packet coprocessors include control logic that supports direct reads of information that summarizes the done status of multiple contexts being handled by the search engine device. This done status information may be maintained in dedicated registers that are configured to support high bandwidth utilization from a data port of the search engine device. The control logic may also be configured to generate interrupts or asynchronous signals that notify an issuing command source of context completion.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: July 25, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Harmeet Bhugra, Michael Miller, John R. Mick, Jr.
  • Patent number: 6785188
    Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: August 31, 2004
    Assignee: Integrated Device Technology, Inc.
    Inventor: John R. Mick
  • Patent number: 6665202
    Abstract: Content addressable memory (CAM) devices include CAM arrays that can identify a best match(es) from a plurality of matches when an operation to compare data applied to a CAM array against data entries within the CAM array is performed. This best match identification operation is preferably performed internal to the CAM array. The best match identification operation does not require operations to determine a highest priority match based on the relative physical locations of multiple matching entries that might be identified within the CAM array during a compare operation. The CAM device also does not require that the CAM array(s) therein be sectored into groups of entry locations (e.g., rows) having ordered priorities or that each CAM array within a multi-array CAM device be treated as a respective sector. Entries having identical priority may be entries having the same number of actively masked bits therein.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: December 16, 2003
    Assignee: Integrated Device Technology, Inc.
    Inventors: Craig A. Lindahl, Yong-Dong Zhao, John R. Mick
  • Patent number: 6591354
    Abstract: A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: July 8, 2003
    Assignee: Integrated Device Technology, Inc.
    Inventors: John R. Mick, Mark W. Baumann
  • Patent number: 6577520
    Abstract: A content addressable memory with programmable priority weighting and low cost match detection is described. A CAM array provides match and no-match indications of an input data word to a weight array. The weight array generates a forced match with an assigned weight that is lower than those assigned to match and no-match indications received from the CAM array. The weight array determines a winning match among the received match indications and the forced match according to their assigned weights, and provides an indication of the winning match to an encoder. The encoder provides an address of the winning match, and a match detect output which is generated from the success or lack thereof of the forced match being determined the winning match.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: June 10, 2003
    Assignee: Integrated Device Technology, Inc.
    Inventor: John R. Mick
  • Patent number: 6567338
    Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: May 20, 2003
    Assignee: Integrated Device Technology, Inc.
    Inventor: John R. Mick
  • Publication number: 20030058671
    Abstract: Content addressable memory (CAM) devices include CAM arrays that can identify a best match(es) from a plurality of matches when an operation to compare data applied to a CAM array against data entries within the CAM array is performed. This best match identification operation is preferably performed internal to the CAM array. The best match identification operation does not require operations to determine a highest priority match based on the relative physical locations of multiple matching entries that might be identified within the CAM array during a compare operation. The CAM device also does not require that the CAM array(s) therein be sectored into groups of entry locations (e.g., rows) having ordered priorities or that each CAM array within a multi-array CAM device be treated as a respective sector. Entries having identical priority may be entries having the same number of actively masked bits therein.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 27, 2003
    Inventors: Craig A. Lindahl, Yong-Dong Zhao, John R. Mick
  • Publication number: 20020154548
    Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.
    Type: Application
    Filed: January 28, 2002
    Publication date: October 24, 2002
    Inventor: John R. Mick
  • Patent number: 6470418
    Abstract: A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first set of match control signals are analyzed. If a match exists in the first CAM array, a first priority encoder is enabled to process the first set of match control signals. If no match exists, the first priority encoder is not enabled, and a second memory cycle is initiated. The second CAM array is enabled during the second memory cycle, and the second set of signals is analyzed. If a match exists in the second CAM array, a second priority encoder is enabled to process the second set of match control signals. If no match exists, the second priority encoder is not enabled.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: October 22, 2002
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Chau-Chin Wu, John R. Mick
  • Patent number: RE40932
    Abstract: A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including either the least significant bit (LSB) or most significant bit (MSB) of the input data value. The CAM array is divided along columns into a similar series of non-overlapping sub-arrays corresponding to the subfields defined by the series of keys. A first CAM sub-array compares the first key with its stored rows of data bit values to generate a first match signal. The first match signal disables each row of the second CAM sub-array for which the corresponding row of the first CAM sub-array did not show a match. A second CAM sub-array then compares the second key with its enabled rows to generate a second match signal.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: October 6, 2009
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Thomas Diede, John R. Mick