Abstract: A server system transmits from an application executing on a virtual client device, through a remote physical client device, a request for a manifest. The server system receives, a manifest received by, and forwarded from, the remote physical client device. The server system determines whether the server system is authorized to modify the received manifest. In response to determining that the server system is authorized to modify the received manifest, the server system requests additional content to modify the received manifest. The server system modifies listed content in the received manifest to generate an updated manifest. The server system sends the updated manifest to the application at the server system. The application processes the updated manifest. The server system sends, to the remote physical client device, an instruction to request the additional content.

Abstract: Systems, apparatuses, and methods are described for protecting the integrity of a playlist, and/or for determining whether a playlist has been altered. The playlist may comprise references to segments of multiple content types. The references may be obfuscated, and/or confirmation data may be used to detect playlist alteration.

Abstract: Systems, apparatuses, and methods are described for protecting the integrity of a playlist, and/or for determining whether a playlist has been altered. The playlist may comprise references to segments of multiple content types. The references may be obfuscated, and/or confirmation data may be used to detect playlist alteration.

Abstract: Systems, apparatuses, and methods are described for protecting the integrity of a playlist, and/or for determining whether a playlist has been altered. The playlist may comprise references to segments of multiple content types. The references may be obfuscated, and/or confirmation data may be used to detect playlist alteration.

Abstract: In one embodiment, a method comprises determining ad placement times for each of a plurality of associated streams. The method also comprises determining an ad selection request time for each of a plurality of ad selection requests based on a cumulative effect of any other ad selection requests occurring at substantially the same time as the determined ad selection time. Each of the plurality of ad selection requests corresponds to one of the plurality of ad placement times.

Abstract: Phone-based remote media system interaction is described. A content distribution system provides a telephone-based voice menu system that enables a caller to select a media system control command. The content distribution system then causes the media system control command to be executed in association with a remote media system associated with, or specified by, the caller.

Abstract: In one embodiment, a method comprises determining ad placement times for each of a plurality of associated streams. The method also comprises determining an ad selection request time for each of a plurality of ad selection requests based on a cumulative effect of any other ad selection requests occurring at substantially the same time as the determined ad selection time. Each of the plurality of ad selection requests corresponds to one of the plurality of ad placement times.

Abstract: In one embodiment, a method can include: (i) receiving a placement opportunity in an ad decision manager (ADM); (ii) sending a request to an ad decision server (ADS); (iii) receiving a conditional response from the ADS, wherein the conditional response includes one or more conditional ads; and (iv) selecting from among the one or more conditional ads.

Abstract: CAM-based search engines may be configured to support multiple databases within a CAM core. These databases may represent tables for different applications, which can be searched sequentially in response to a single indirect instruction that is loaded during a control cycle. The databases to be searched may be identified by a multi-database search instruction that is loaded during a single data cycle, which may overlap with the control cycle. In some cases, the databases may be searched using variations of a primary search key, so that it is unnecessary to repeatedly load the entire search key across a network interface for each search operation within a respective database. Instead, shorter replacement key segments may be loaded for each of a plurality of the search operations and these replacement key segments may be combined with one or more segments of the primary search key in the CAM core to define a desired search key for a respective search operation.

Abstract: CAM-based search engine devices operate to reduce the occurrence of duplicate learned entries within a CAM database when processing search and learn (SNL) instructions. A search engine device may be configured to support processing of first and second immediately consecutive and equivalent SNL instructions as a first SNL instruction and a second search and search instruction, respectively. This processing is performed in order to block an addition of a duplicate learned entry within a database in the search engine device. The search engine device may also be configured to selectively block processing of the second SNL instruction as a second search and search instruction in response to detecting the database as full when the first SNL instruction is processed.

Abstract: An integrated circuit chip includes a search engine including a content addressable memory (CAM) configured to produce CAM indices responsive to search instructions provided to the search engine. The search engine further includes an index translation circuit operatively coupled to the CAM and configured to provide translation of the CAM indices to another memory space, such as from an absolute index space associated with the CAM to a memory space associated with a database within the CAM or to a memory space of a device external to the chip, such as a command source or external SRAM.

Abstract: CAM-based search engines may be configured to support multiple databases within a CAM core. These databases may represent tables for different applications, which can be searched sequentially in response to a single indirect instruction that is loaded during a control cycle. The databases to be searched may be identified by a multi-database search instruction that is loaded during a single data cycle, which may overlap with the control cycle. In some cases, the databases may be searched using variations of a primary search key, so that it is unnecessary to repeatedly load the entire search key across a network interface for each search operation within a respective database. Instead, shorter replacement key segments may be loaded for each of a plurality of the search operations and these replacement key segments may be combined with one or more segments of the primary search key in the CAM core to define a desired search key for a respective search operation.

Abstract: Integrated search engine devices include a content addressable memory (CAM) core that is configured to support at least one database of searchable entries therein and a control circuit. The control circuit is configured to support reporting to a command host of data identifying entries that have been aged out of the at least one database and/or entries that have exceeded an activity-based aging threshold. The control circuit is further configured to support age reporting that is programmable on a per entry basis within the at least one database.

Abstract: CAM-based search engines and packet coprocessors include control logic that supports direct reads of information that summarizes the done status of multiple contexts being handled by the search engine device. This done status information may be maintained in dedicated registers that are configured to support high bandwidth utilization from a data port of the search engine device. The control logic may also be configured to generate interrupts or asynchronous signals that notify an issuing command source of context completion.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: Content addressable memory (CAM) devices include CAM arrays that can identify a best match(es) from a plurality of matches when an operation to compare data applied to a CAM array against data entries within the CAM array is performed. This best match identification operation is preferably performed internal to the CAM array. The best match identification operation does not require operations to determine a highest priority match based on the relative physical locations of multiple matching entries that might be identified within the CAM array during a compare operation. The CAM device also does not require that the CAM array(s) therein be sectored into groups of entry locations (e.g., rows) having ordered priorities or that each CAM array within a multi-array CAM device be treated as a respective sector. Entries having identical priority may be entries having the same number of actively masked bits therein.

Abstract: A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

Abstract: A content addressable memory with programmable priority weighting and low cost match detection is described. A CAM array provides match and no-match indications of an input data word to a weight array. The weight array generates a forced match with an assigned weight that is lower than those assigned to match and no-match indications received from the CAM array. The weight array determines a winning match among the received match indications and the forced match according to their assigned weights, and provides an indication of the winning match to an encoder. The encoder provides an address of the winning match, and a match detect output which is generated from the success or lack thereof of the forced match being determined the winning match.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including either the least significant bit (LSB) or most significant bit (MSB) of the input data value. The CAM array is divided along columns into a similar series of non-overlapping sub-arrays corresponding to the subfields defined by the series of keys. A first CAM sub-array compares the first key with its stored rows of data bit values to generate a first match signal. The first match signal disables each row of the second CAM sub-array for which the corresponding row of the first CAM sub-array did not show a match. A second CAM sub-array then compares the second key with its enabled rows to generate a second match signal.