Abstract: The combination of a seven-port random access memory (RAM) unit, a funnel shifter, a mask generator, an arithmetic logic unit (ALU), a merge logic unit, a number of multiplexers, and three bi-directional data buses are configured to form a thirty-two bit, cascadable, microprogrammable, bit-slice suitable for executing complex operations such as those which require that several operands be read from the memory unit, be rotated in the funnel shifter, be operated upon by the arithmetic logic unit, be merged in the merge logic unit, and the result be written back into the memory unit all in a single cycle.

Abstract: An emulator for non-fixed instruction set VLSI devices having a microprogrammable emulator controller which can be used with a variety of VLSI devices and provide in-circuit emulation for general VLSI technology with capabilities comparable to the in-channel emulation capabilities previously available for fixed instruction set MOS microprocessors. This includes a device specific emulator head which is controlled by the emulator controller to emulate a VLSI device in a target machine. The VLSI device to be emulated is removed from the target machine and a device plug of the emulator head is inserted into the target machine. The VLSI device is placed in a socket in the emulator head. The emulator controller monitors instructions sent from the target machine to the VLSI device and provides instructions to the VLSI device.

Abstract: A processor, used in microcomputer systems for performing data processing functions, includes an arithmetic-logic unit having three operand inputs to provide the capability of executing, in addition to typical arithmetic and logic operations, complex three-operand instructions in a single clock (instruction) cycle.

Abstract: A microprogram controller, in a microcomputer system used as an address sequencer intended for controlling the sequence of execution of microinstructions in a microprogram memory, is presented. The microprogram controller includes architecture that provides the capability to asynchronously receive indications of an event, break from the microinstruction sequence in response, branch to control of subroutine consisting of a predetermined microinstruction sequence directed to responding to the event, and returning to the interrupted sequence upon completion of the subroutine.