Patents by Inventor John S. Dodson
John S. Dodson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11017875Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.Type: GrantFiled: March 25, 2019Date of Patent: May 25, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
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Patent number: 10971246Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.Type: GrantFiled: April 18, 2019Date of Patent: April 6, 2021Assignee: International Business Machines CorporationInventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
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Patent number: 10649511Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: GrantFiled: April 29, 2019Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Irving G Baysah, John S Dodson, Karthick Rajamani, Eric E Retter, Scot H Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S Allen-Ware
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Publication number: 20190250682Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Irving G. Baysah, John S. Dodson, Karthick Rajamani, Eric E. Retter, Scot H. Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S. Allen-Ware
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Publication number: 20190244676Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Inventors: JOHN S. DODSON, MARC A. GOLLUB, WARREN E. MAULE, BRAD W. MICHAEL
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Publication number: 20190221280Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Inventors: JOHN S. DODSON, MARC A. GOLLUB, WARREN E. MAULE, BRAD W. MICHAEL
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Patent number: 10353669Abstract: Managing entries in a mark table of computer memory errors including identifying at least two mark table entries as candidates for merger, wherein each mark table entry indicates an error at a location in a computer memory; and merging the identified mark table entries into a single mark table entry, including removing one of the identified mark table entries from the mark table.Type: GrantFiled: September 2, 2016Date of Patent: July 16, 2019Assignee: International Business Machines CorporationInventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
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Patent number: 10338999Abstract: Confirming memory marks indicating an error in computer memory including detecting, by memory logic responsive to a memory read operation, an error in at a memory location; marking, by the memory logic in an entry in a hardware mark table, the memory location as containing the error, the entry including one or more parameters for correcting the error; and retrying, by the memory logic, the memory read operation, including: responsive to again detecting the error in the memory location, determining whether the error is correctable at the memory location using the parameters included in the entry; and if the error is correctable at the memory location using the one or more parameters included in the entry, confirming the error in the entry of the hardware mark table.Type: GrantFiled: September 2, 2016Date of Patent: July 2, 2019Assignee: International Business Machines CorporationInventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
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Patent number: 10317964Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: GrantFiled: January 5, 2016Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Irving G Baysah, John S Dodson, Karthick Rajamani, Eric E Retter, Scot H Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S Allen-Ware
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Patent number: 10304560Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.Type: GrantFiled: September 2, 2016Date of Patent: May 28, 2019Assignee: International Business Machines CorporationInventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
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Patent number: 10297335Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.Type: GrantFiled: September 2, 2016Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
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Patent number: 10176125Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.Type: GrantFiled: December 1, 2017Date of Patent: January 8, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John S. Dodson, Didier R. Louis, Eric E. Retter, Jeffrey A. Stuecheli
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Patent number: 10019370Abstract: A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.Type: GrantFiled: July 1, 2016Date of Patent: July 10, 2018Assignee: International Business Machines CorporationInventors: Bulent Abali, John S. Dodson, Moinuddin K. Qureshi, Balaram Sinharoy
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Publication number: 20180121375Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.Type: ApplicationFiled: December 1, 2017Publication date: May 3, 2018Inventors: JOHN S. DODSON, DIDIER R. LOUIS, ERIC E. RETTER, JEFFREY A. STUECHELI
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Publication number: 20180067806Abstract: Confirming memory marks indicating an error in computer memory including detecting, by memory logic responsive to a memory read operation, an error in at a memory location; marking, by the memory logic in an entry in a hardware mark table, the memory location as containing the error, the entry including one or more parameters for correcting the error; and retrying, by the memory logic, the memory read operation, including: responsive to again detecting the error in the memory location, determining whether the error is correctable at the memory location using the parameters included in the entry; and if the error is correctable at the memory location using the one or more parameters included in the entry, confirming the error in the entry of the hardware mark table.Type: ApplicationFiled: September 2, 2016Publication date: March 8, 2018Inventors: JOHN S. DODSON, MARC A. GOLLUB, WARREN E. MAULE, BRAD W. MICHAEL
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Publication number: 20180067798Abstract: Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.Type: ApplicationFiled: September 2, 2016Publication date: March 8, 2018Inventors: JOHN S. DODSON, MARC A. GOLLUB, WARREN E. MAULE, BRAD W. MICHAEL
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Publication number: 20180067719Abstract: Managing entries in a mark table of computer memory errors including identifying at least two mark table entries as candidates for merger, wherein each mark table entry indicates an error at a location in a computer memory; and merging the identified mark table entries into a single mark table entry, including removing one of the identified mark table entries from the mark table.Type: ApplicationFiled: September 2, 2016Publication date: March 8, 2018Inventors: JOHN S. DODSON, MARC A. GOLLUB, WARREN E. MAULE, BRAD W. MICHAEL
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Publication number: 20180068741Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.Type: ApplicationFiled: September 2, 2016Publication date: March 8, 2018Inventors: JOHN S. DODSON, MARC A. GOLLUB, WARREN E. MAULE, BRAD W. MICHAEL
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Patent number: 9892066Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.Type: GrantFiled: October 31, 2016Date of Patent: February 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John S. Dodson, Didier R. Louis, Eric E. Retter, Jeffrey A. Stuecheli
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Patent number: 9684461Abstract: A memory system comprises memory devices coupled to a memory controller via a memory interface bus, the memory controller for receiving one or more memory requests via an interconnect. The memory controller tracks utilization of the memory interface bus for reads from the memory devices for a selection of the one or more memory requests during a time window. The memory controller, responsive to detecting utilization of the memory interface bus for reads during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of data to be accessed from the memory devices by at least one read operation, the reduced data size selected from among at least two read data size options for the at least one read operation of a maximum read data size and the reduced read data size that is less than the maximum read data size.Type: GrantFiled: October 31, 2016Date of Patent: June 20, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John S. Dodson, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli