Abstract: A circuit for configuring a Plug and Play expansion card in one of three ways. The first is the standard Plug and Play configuration method, wherein expansion cards go through the isolation process to obtain unique Card Select Numbers (CSN). This method requires the existence of a dedicated serial EEPROM to store the system resource data for the expansion cards. However, when an expansion card is directly mounted onto a system board, it becomes a system board device. This allows the separate serial EEPROM to be removed. To implement, two alternative configuration modes are provided, wherein the expansion card can be configured under main CPU control. In these alternative modes, the configuration data is stored in the main system BIOS ROM. In the first mode, a register in the expansion card is mapped to a fixed ISA I/O address. In the second mode, the register is controlled by a dedicated pin, thus allowing it to be mapped to any ISA I/O address.

Abstract: A system utilizes one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined criteria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a keyboard controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

Abstract: A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with applications software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to evaluate external addresses for a preset interval, preventing the processor from accessing the cache, thereby slowing down the processor. The external address evaluation direction is released when a bus requesting device indicates a bus request during the slowdown, allowing the processor to respond to the bus request promptly to prevent possible latency problems from occurring, but still maintaining the processor in a halted state.

Abstract: A system utilizes one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined citeria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a keyboard controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.

Abstract: A memory controller has an asynchronous portion and a synchronous portion. The synchronous portion is used when the system processor is accessing the memory, while the asynchronous portion is used when control of the memories is held by a DMA controller or a bus master located on a standardized bus.

Abstract: A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems in which each processing module has a local cache. Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibited by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.