Abstract: Local input/output (LIO) lines may be used for precharging and equalizing the digit lines associated with a sense amplifier. The precharge device and equalization device of the associated sense amplifier may be omitted in some examples. In some examples, an equalization device may short the lines of a LIO line pair together. The LIO line pair may drive one or more pairs of digit lines to a precharge potential. Digit lines may be connected to the LIO line pair and driven to a midpoint potential in some examples.

Abstract: In some examples, a main word line driver may include a transistor that is driven between an on state and a high resistance state by a signal based, at least in part, on a row address. In both states, the transistor may maintain a main word line in an inactive state. When in the high resistance state, the transistor may be overridden by a decoder that drives the main word line to an active state. In some examples, a main word line driver may include a transistor maintained in a high resistance state coupled in parallel with another transistor that may be driven between an on state and an off state by a signal based, at least in part, on a row address. When the other transistor is in the off state, the high resistance state transistor may be overridden by a decoder that drives a main word line to an active state.

Abstract: Components of sense amplifiers may share contacts that couple the components to a global line via a local line. In some examples, the components may be pull-down circuits of a same sense amplifier or pull-down circuits of adjacent sense amplifiers. The shared contact may include a transistor or a resistance between the local line and the global line. In some examples, the global line may be an RNL line. The transistor or resistance may reduce the impact of voltage across the components from affecting the global line and/or reduce the impact of voltage changes on the global line on the individual components.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

Abstract: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

Abstract: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

Abstract: Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndromes are generated and stored. When transitioning from the reduced power refresh mode, data from the rows of memory cells are read, and the stored syndromes are used to determine if there are errors in the read data. The syndromes are also used to correct any errors that are found, and the corrected data are written to the rows of memory cells. By correcting any errors that exist when transitioning from the reduced power refresh mode, it is not necessary to use the syndromes to detect and correct errors while operating in the reduced power refresh mode.