Abstract: A method and apparatus are described which provide a memory device with sense amplifiers extending in a first direction and corresponding digit lines extending in a second direction perpendicular to the first direction. A pair of complementary digit lines may originate from different memory sub-arrays. The arrangement is particular useful for memory arrays having 6F**2 feature size.

Abstract: A memory device having banks of sense amplifiers with two different types of sense amplifiers is provided. A first driver used to activate the first type of sense amplifier is embedded into a first bank. A second driver used to activate a second type of sense amplifier is embedded into a second bank. This alternating physical placement of the first and second sense amplifier drivers within respective banks is repeated throughout the device. This alternating physical arrangement frees up the gaps and mini-gaps for other functions, reduces the buses used for sense amplifier activation signals and allows large drivers to be used, which improves the operation of the sense amplifiers and the device itself.

Abstract: Devices and methods for enhancing decoding a non-volatile memory device are discussed. One aspect of the present invention includes a method for decoding a non-volatile memory device. The method includes decoding a set of input signals to present a row decoded signal; driving a node by a driver that receives the decoded signal; transferring a negative supply to a word line by a transfer mechanism; and limiting a rate of flow of electric charge from the negative supply to the word line so as to inhibit an undesired rate of flow of electric charge from the negative supply to the word line.

Abstract: A memory device having banks of sense amplifiers comprising two types of sense amplifiers. A first driver used to activate the first type of sense amplifier is embedded into a first bank. A second driver used to activate a second type of sense amplifier is embedded into a second bank. This alternating physical placement of the first and second sense amplifier drivers within respective banks is repeated throughout the device. This alternating physical arrangement frees up the gaps and mini-gaps for other functions, reduces the buses used for sense amplifier activation signals and allows large drivers to be used, which improves the operation of the sense amplifiers and the device itself.

Abstract: A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to a local supply node, which during standby conditions when the word line driver circuit is not driving a word line, is maintained at a voltage less than that of a global power supply node. In one embodiment, the local power supply node is coupled to the global power supply node by means of at least one decoupling transistor receiving a control signal at its gate and by a vt-connected transistor, such that the voltage on the local power supply node is maintained at a level not exceeding one transistor threshold voltage less than the global power supply node voltage when the decoupling transistor is off.

Abstract: Devices and methods for enhancing decoding a non-volatile memory device are discussed. One aspect of the present invention includes a method for decoding a non-volatile memory device. The method includes decoding a set of input signals to present a row decoded signal; driving a node by a driver that receives the decoded signal; transferring a negative supply to a word line by a transfer mechanism; and limiting a rate of flow of electric charge from the negative supply to the word line so as to inhibit an undesired rate of flow of electric charge from the negative supply to the word line.

Abstract: A method and apparatus are described which provide a memory device with sense amplifiers extending in a first direction and corresponding digit lines extending in a second direction perpendicular to the first direction. A pair of complementary digit lines may originate from different memory sub-arrays. The arrangement is particular useful for memory arrays having 6F**2 feature size.

Abstract: A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to a local supply node, which during standby conditions when the word line driver circuit is not driving a word line, is maintained at a voltage less than that of a global power supply node. In one embodiment, the local power supply node is coupled to the global power supply node by means of at least one decoupling transistor receiving a control signal at its gate and by a vt-connected transistor, such that the voltage on the local power supply node is maintained at a level not exceeding one transistor threshold voltage less than the global power supply node voltage when the decoupling transistor is off.

Abstract: A method and apparatus are described which provide a memory device with sense amplifiers extending in a first direction and corresponding digit lines extending in a second direction perpendicular to the first direction. A pair of complementary digit lines may originate from different memory sub-arrays. The arrangement is particular useful for memory arrays having 6F**2 feature size.