Patents by Inventor John Smythe

John Smythe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013305
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
  • Publication number: 20200373307
    Abstract: A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe
  • Publication number: 20200357682
    Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Scott L. Light, John A. Smythe, Sony Varghese
  • Publication number: 20200295011
    Abstract: A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe
  • Patent number: 10777562
    Abstract: A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe
  • Patent number: 10770465
    Abstract: A method used in forming integrated circuitry comprises forming a substrate comprising a conductive line structure comprising opposing longitudinal sides individually comprising a sacrificial material that is laterally between insulator material. The sacrificial material comprises metal oxide. At least some of the sacrificial material is removed to form an upwardly-open void space laterally between the insulator material on the opposing longitudinal sides of the conductive line structure. The void space is covered with insulating material to leave a sealed void space beneath the insulating material on the opposing longitudinal sides of the conductive line structure. Other embodiments are disclosed.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Richard J. Hill, John A. Smythe, Gurtej S. Sandhu
  • Patent number: 10763155
    Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Scott L. Light, John A. Smythe, Sony Varghese
  • Publication number: 20200251349
    Abstract: Systems, apparatuses, and methods related to reduction of crystal growth resulting from annealing a conductive material are described. An example apparatus includes a conductive material selected to have an electrical resistance that is reduced as a result of annealing. A stabilizing material may be formed over a surface of the conductive material. The stabilizing material may be selected to have properties that include stabilization of the reduced electrical resistance of the conductive material and reduction of a degree of freedom of crystal growth relative to the surface resulting from recrystallization of the conductive material during the annealing.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: Marko Milojevic, John A. Smythe, III
  • Publication number: 20200251334
    Abstract: Methods, apparatuses, and systems related to formation of an atomic layer of germanium (Ge) on a substrate material are described. An example method includes introducing, into a semiconductor processing chamber housing a substrate material having a high aspect ratio, a reducing agent, and introducing, into the semiconductor processing chamber, a germanium amidinate precursor. The example method further includes forming an atomic layer of germanium on the substrate material resulting from a reaction of the reducing agent and the germanium amidinate precursor.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: Francois H. Fabreguette, Paul A. Paduano, Gurtej S. Sandhu, John A. Smythe, III, Matthew N. Rocklein
  • Publication number: 20200243339
    Abstract: A method of doping a silicon-containing material. The method comprises forming at least one opening in a silicon-containing material and conformally forming a doped germanium material in the at least one opening and adjacent to the silicon-containing material. A dopant of the doped germanium material is transferred into the silicon-containing material. Methods of forming a semiconductor device are also disclosed, as are semiconductor devices comprising a doped silicon-containing material.
    Type: Application
    Filed: January 24, 2019
    Publication date: July 30, 2020
    Inventors: Francois H. Fabreguette, John A. Smythe, Witold Kula
  • Publication number: 20200235005
    Abstract: Apparatus (e.g., semiconductor devices) include stack structures with at least one conductive region and at least one nonconductive material. A multidielectric spacer is adjacent the at least one conductive region and comprises first and second dielectric materials. The first dielectric material, adjacent the at least one conductive region, includes silicon and nitrogen. The second dielectric material, adjacent the first dielectric material, comprises silicon-carbon bonds and defines a substantially straight, vertical, outer sidewall. In methods to form such apparatus, the first dielectric material may be formed with selectivity on the at least one conductive region, and the second dielectric material may be formulated and formed to exhibit etch resistance.
    Type: Application
    Filed: January 17, 2019
    Publication date: July 23, 2020
    Inventors: John A. Smythe, Silvia Borsari, Francois H. Fabreguette, Sutharsan Ketharanathan
  • Patent number: 10656354
    Abstract: A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to the photonic device using a lens between the two which is moveable by actuator heads. The lens is moveable by respective motive sources associated with the actuator heads.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Roy Meade, Lei Bi, John Smythe
  • Patent number: 10643906
    Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, John A. Smythe, Haitao Liu, Richard J. Hill, Deepak Chandra Pandey
  • Publication number: 20200066917
    Abstract: A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Inventors: Witold Kula, Gurtej S. Sandhu, John A. Smythe
  • Patent number: 10504917
    Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control-gate regions. Charge-storage material of individual memory cells extend elevationally along individual of the control-gate regions of the wordline levels and do not extend elevationally along the insulative levels. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions of the wordline levels laterally through which charge migration between the individual control-gate regions and the charge-storage material is blocked. Channel material extends elevationally along the stack and is laterally spaced from the charge-storage material by insulative charge-passage material.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Richard J. Hill, John A. Smythe
  • Publication number: 20190313680
    Abstract: The present invention relates to methods for modifying or enhancing a flavor of a food or beverage product, and to flavored food and beverage products With a modified or enhanced flavor.
    Type: Application
    Filed: December 13, 2017
    Publication date: October 17, 2019
    Applicant: Tate & Lyle Ingredients Americas LLC
    Inventors: Joshua Nehemiah Fletcher, John Smythe
  • Publication number: 20190297932
    Abstract: Processes for the preparation of glycosylated steviol glycoside compositions useful sweeteners and flavor modifiers in food and beverage products and the like are improved by the use of basic conditions before, during and/or after an enzyme-catalyzed glycosylation of a steviol glycoside composition.
    Type: Application
    Filed: June 5, 2017
    Publication date: October 3, 2019
    Applicant: Tate & Lyle Ingredients Americas LLC
    Inventors: Joshua Fletcher, Ryan Woodyer, Mikhail Gololobov, Ryan Gross, John Smythe, Salma Siraj, Xian Chen, James Gaddy
  • Patent number: 10388872
    Abstract: A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. A second portion of the dielectric material is formed on and between the discrete conductive particles by atomic layer deposition. A memory cell material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe
  • Publication number: 20190239540
    Abstract: Tri- and tetra-saccharides are used in foods, beverages and other consumable products to mask or reduce the unpleasant taste of certain components also present in such products, such as the bitter taste of certain high intensity sweeteners. The organoleptic qualities of the products are thereby improved. In particular, melezitose, maltotriose and maltotetraose effectively reduce the bitterness of consumable products containing steviol glycosides such as rebaudioside A.
    Type: Application
    Filed: August 31, 2017
    Publication date: August 8, 2019
    Applicant: Tate & Lyle Ingredients Americas LLC
    Inventors: Mikhail Gololobov, Joshua Fletcher, John Smythe, Ryan D. Woodyer
  • Publication number: 20190206723
    Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Ken Tokashiki, John A. Smythe, Gurtej S. Sandhu