Patents by Inventor John Stephenson

John Stephenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006794
    Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Application
    Filed: September 13, 2024
    Publication date: January 2, 2025
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
  • Patent number: 12173574
    Abstract: A wellbore tubular flotation device comprises a housing having a locking element disposed thereon. The housing is shaped to move through an interior of a wellbore tubular segment. The locking element is shaped to engage the interior of the wellbore tubular segment. The locking element comprises a locking mechanism configured to urge the locking element into contact with the interior of the wellbore tubular. A burst disk is engaged with the housing and is shaped to close the tubular segment to fluid flow. A release mechanism is configured to reverse the urging of the locking mechanism when a release tool is moved through the housing.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: December 24, 2024
    Assignee: Deep Casing Tools, Ltd.
    Inventors: David John Stephenson, Tomasz Jozef Walerianczyk
  • Patent number: 12142641
    Abstract: A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: November 12, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Publication number: 20240358958
    Abstract: A headgear system and/or an interface assembly incorporating a headgear system that, in some configurations, is configured to transform from elasticated or “stretchy” behavior to “inelastic” behavior at least in response to normal or expected forces encountered during the intended therapy. In some configurations, upon fitment to the head of a user, the system automatically adjusts toward or to an appropriate size. A headgear portion or assembly for use in combination with a breathing apparatus in some configurations is at least substantially inelastic and is three dimensional in shape. The headgear portion or assembly can comprise a plastic core and a textile casing. The headgear, or part thereof, may also have integrally moulded labels, connectors, adjustment mechanisms and/or grips.
    Type: Application
    Filed: April 9, 2024
    Publication date: October 31, 2024
    Inventors: Brett John Huddart, Jeroen Hammer, Matthew Robert Geoff Slight, Vitaly Kapelevich, David Monroy Felix, Callum Ross Gordon, Bruce Michael Walls, Melissa Catherine Bornholdt, Matthew Roger Stephenson, Paul Mathew Freestone, Ryan Anthony Graham, Mark Arvind McLaren
  • Patent number: 12128183
    Abstract: Patient interface components and/or associated head gear and adjustment systems improve sealing and/or patient comfort and/or ease of use. The interface includes an inflating or ballooning seal. The headgear assembly can be connected to the interface with an elastic component and an inelastic component. The elastic component enabling a course fitting of the interface to the patient and the inelastic component enabling a final fitting of the interface to the patient.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: October 29, 2024
    Assignee: Fisher & Paykel Healthcare Limited
    Inventors: Daniel John Smith, Brett John Huddart, Matthew James Adams, Nicholas Alexander Hobson, Timothy James Beresford Sharp, Roheet Patel, Gregory James Olsen, Matthew Roger Stephenson, Troy Barsten
  • Patent number: 12119380
    Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: October 15, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Patent number: 12102759
    Abstract: A respiratory mask can include one or a plurality of force sensors configured to detect a force imparted to a user's skin. Output from the one or more sensors can be represented in a way useful to the patient or healthcare provider for adjusting the mask to achieve a desired fitment. A representation of the detected forces can be displayed on a separate display device or on the mask.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: October 1, 2024
    Assignee: Fisher & Paykel Healthcare Limited
    Inventors: Fadi Karim Moh'd Mashal, Matthew Roger Stephenson, Jeroen Hammer, Daniel John Smith, Jonathan David Harwood
  • Patent number: 12102765
    Abstract: A headgear system and/or an interface assembly incorporating a headgear system that, in some configurations, is configured to transform from elasticated or “stretchy” behavior to “inelastic” behavior at least in response to normal or expected forces encountered during the intended therapy. In some configurations, upon fitment to the head of a user, the system automatically adjusts toward or to an appropriate size. A headgear portion or assembly for use in combination with a breathing apparatus in some configurations is at least substantially inelastic and is three dimensional in shape. The headgear portion or assembly can comprise a plastic core and a textile casing. The headgear, or part thereof, may also have integrally moulded labels, connectors, adjustment mechanisms and/or grips.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: October 1, 2024
    Assignee: Fisher & Paykel Healthcare Limited
    Inventors: Brett John Huddart, Jeroen Hammer, Matthew Robert Geoff Slight, Vitaly Kapelevich, David Monroy Felix, Callum Ross Gordon, Bruce Michael Walls, Melissa Catherine Bornholdt, Matthew Roger Stephenson, Paul Mathew Freestone, Ryan Anthony Graham, Mark Arvind McLaren
  • Publication number: 20240318731
    Abstract: A seat carrier subassembly for a valve includes first and second ring components assembled over an O-ring seal, wherein a portion of the O-ring seal is exposed in an inner diameter gap between inner edge portions of the first and second ring components to define a seat seal.
    Type: Application
    Filed: April 25, 2024
    Publication date: September 26, 2024
    Inventors: David John Owen Parkes, Barry Cannell Irvine, Graham Harwood Stephenson, Charles Kneen Bregazzi
  • Publication number: 20240194740
    Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: February 19, 2024
    Publication date: June 13, 2024
    Inventors: KEITH DORAN WEEKS, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Patent number: 11978771
    Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: May 7, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Publication number: 20240068311
    Abstract: A wellbore tubular flotation device comprises a housing having a locking element disposed thereon. The housing is shaped to move through an interior of a wellbore tubular segment. The locking element is shaped to engage the interior of the wellbore tubular segment. The locking element comprises a locking mechanism configured to urge the locking element into contact with the interior of the wellbore tubular. A burst disk is engaged with the housing and is shaped to close the tubular segment to fluid flow. A release mechanism is configured to reverse the urging of the locking mechanism when a release tool is moved through the housing.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: David John Stephenson, Tomasz Jozef Walerianczyk
  • Publication number: 20240063268
    Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 22, 2024
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
  • Patent number: 11848356
    Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 19, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Patent number: 11837634
    Abstract: A semiconductor device may include a semiconductor layer and a superlattice adjacent the semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 5, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Patent number: 11828119
    Abstract: A wellbore tubular flotation device comprises a housing having a locking element disposed thereon. The housing is shaped to move through an interior of a wellbore tubular segment. The locking element is shaped to engage the interior of the wellbore tubular segment. The locking element comprises a locking mechanism configured to urge the locking element into contact with the interior of the wellbore tubular. A burst disk is engaged with the housing and is shaped to close the tubular segment to fluid flow. A release mechanism is configured to reverse the urging of the locking mechanism when a release tool is moved through the housing.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: November 28, 2023
    Assignee: Deep Casing Tools, Ltd.
    Inventors: David John Stephenson, Tomasz Jozef Walerianczyk
  • Patent number: 11664427
    Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: May 30, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
  • Patent number: 11664459
    Abstract: A method for making a semiconductor device may include forming an inverted T channel on a substrate, with the inverted T channel comprising a superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source and drain regions on opposing ends of the inverted T channel, and forming a gate overlying the inverted T channel between the source and drain.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: May 30, 2023
    Assignee: ATOMERA INCORPORATED
    Inventor: Robert John Stephenson
  • Publication number: 20230121774
    Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
  • Publication number: 20230122723
    Abstract: A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI