Patents by Inventor John Stephenson

John Stephenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11075078
    Abstract: A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: July 27, 2021
    Assignee: ATOMERA INCORPORATED
    Inventors: Nyles Wynn Cody, Keith Doran Weeks, Robert John Stephenson, Richard Burton, Yi-Ann Chen, Dmitri Choutov, Hideki Takeuchi, Yung-Hsuan Yang
  • Publication number: 20210074814
    Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Inventors: ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J. MEARS, ERWIN TRAUTMANN
  • Patent number: 10934796
    Abstract: A method for recovering a conduit from a wellbore includes positioning an expander tool having at least one biasing element within the conduit an expander tool and exerting a force against the at least one biasing element to radially expand the conduit to an amount sufficient to fracture solids outside of and in contact with the conduit.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 2, 2021
    Assignee: Deep Casing Tools, Ltd.
    Inventors: David John Stephenson, Tomasz Jozef Walerianczyk, Neil Andrew Abercrombie Simpson
  • Patent number: 10884185
    Abstract: A semiconductor device may include a substrate having waveguides thereon, and a superlattice overlying the substrate and waveguides. The superlattice may include stacked groups of layers, with each group of layers comprising a stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include an active device layer on the superlattice including at least one active semiconductor device.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 5, 2021
    Assignee: ATOMERA INCORPORATED
    Inventor: Robert John Stephenson
  • Publication number: 20200411645
    Abstract: A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON
  • Patent number: 10879356
    Abstract: A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
  • Patent number: 10811498
    Abstract: A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 20, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Patent number: 10777451
    Abstract: A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 15, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J Mears, Erwin Trautmann
  • Patent number: 10763370
    Abstract: A semiconductor device may include a substrate and an inverted T channel on the substrate and including a superlattice. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include source and drain regions on opposing ends of the inverted T channel, and a gate overlying the inverted T channel between the source and drain regions.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: September 1, 2020
    Assignee: ATOMERA INCORPORATED
    Inventor: Robert John Stephenson
  • Patent number: 10741436
    Abstract: A method for making a semiconductor device may include forming first and second spaced apart shallow trench isolation (STI) regions in a semiconductor substrate, and forming a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a first semiconductor stringer comprising a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and forming a gate above the superlattice.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: August 11, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Scott A. Kreps, Robert J. Mears, Kalipatnam Vivek Rao
  • Patent number: 10727049
    Abstract: A method for making a semiconductor device may include forming a recess in a substrate including a first Group IV semiconductor, forming an active layer comprising a Group III-V semiconductor within the recess, and forming a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The method may further include forming an impurity and point defect blocking superlattice layer adjacent the buffer layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 28, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Publication number: 20200224403
    Abstract: Method and system for treatment of a wastewater stream at a location is disclosed. The wastewater stream includes a floating waste component such as sewer FOG or oil and an aqueous component such as water. The wastewater stream is directed from the location to a separator through an intake which is fluidly connected to the location and the separator. The separator separates the floating waste component from the aqueous component. The separated floating waste component is directed to a floating waste discharge outlet associated with the separator and the separated aqueous component is directed to an aqueous discharge outlet associated with the separator.
    Type: Application
    Filed: January 31, 2018
    Publication date: July 16, 2020
    Inventors: Peter Douglas JACK, Robert John STEPHENSON, Michael Stephen GARDNER
  • Publication number: 20200135489
    Abstract: A method for making a semiconductor device may include forming a superlattice layer and an adjacent semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include diffusing nitrogen into the superlattice layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, LOUIS NICHOLAS HUTTER, III
  • Publication number: 20200075327
    Abstract: A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, an upper portion of at least one of the base semiconductor portions adjacent the respective at least one non-semiconductor monolayer may have a defect density less than or equal to 1×105/cm2.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: Keith Doran WEEKS, Nyles Wynn CODY, Marek HYTHA, Robert J. MEARS, Robert John STEPHENSON
  • Publication number: 20200075731
    Abstract: A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: KEITH DORAN WEEKS, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Patent number: 10566191
    Abstract: A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, an upper portion of at least one of the base semiconductor portions adjacent the respective at least one non-semiconductor monolayer may have a defect density less than or equal to 1×105/cm2.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 18, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Publication number: 20190352195
    Abstract: A method and system for removing at least dissolved hydrogen sulphide or another targeted constituent from a feedstock is provided wherein the targeted constituent has a gas: liquid equilibrium. In some embodiments, the method includes the steps of: contacting the feedstock in at least one stripping vessel with a stripping gas to produce a gas stream containing at least hydrogen sulphide gas; conveying the gas stream from the at least one stripping vessel to an oxidation reactor; contacting the gas stream with an oxidizing agent in the oxidation reactor so as to oxidize the at least hydrogen sulphide gas to produce sulphuric acid; and conveying the produced sulphuric acid from the oxidation reactor to the at least one stripping vessel so as to reduce a pH value of the feedstock within the stripping vessel.
    Type: Application
    Filed: January 3, 2018
    Publication date: November 21, 2019
    Applicant: Muddy River Technologies Inc.
    Inventors: Robert John STEPHENSON, Peter Douglas JACK
  • Publication number: 20190345787
    Abstract: A method for recovering a conduit from a wellbore includes positioning an expander tool having at least one biasing element within the conduit an expander tool and exerting a force against the at least one biasing element to radially expand the conduit to an amount sufficient to fracture solids outside of and in contact with the conduit.
    Type: Application
    Filed: November 15, 2018
    Publication date: November 14, 2019
    Inventors: David John Stephenson, Tomasz Jozef Walerianczyk, Neil Andrew Abercrombie Simpson
  • Patent number: 10468245
    Abstract: A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The semiconductor device may further include an impurity and point defect blocking superlattice layer adjacent the buffer layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: November 5, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Publication number: 20190330086
    Abstract: An electrocoagulation unit for removing one or more dissolved constituents from an untreated feedstock comprises a non-electrically conductive housing having a fluid inlet, a fluid outlet and an interior surface; a cathode and anode arranged within the housing, the cathode and anode each having an ionizing surface, the ionizing surfaces of the anode and cathode in opposed facing relation so as to define a gap having a separation distance therebetween; the cathode and the anode configured to be electrically coupled to a DC power supply in a DC electrical circuit so as to ionize and dissolve the ionizing surface of the anode; and a controller configured to maintain the separation distance at a set value as the ionizing surface of the anode dissolves. A method for using a plurality of electrocoagulation units in series is also provided.
    Type: Application
    Filed: January 3, 2018
    Publication date: October 31, 2019
    Inventors: Robert John STEPHENSON, Michael Stephen GARDNER, Peter Douglas JACK