Patents by Inventor John T. Gasner
John T. Gasner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8963266Abstract: A device having a detector includes a sensor package. The sensor package includes a light sensor, at least one filter located over the light sensor and at least one bond pad. The light sensor is formed on a semiconductor device that provides sensor information related to light incident upon the light sensor. A perimeter of each bond pad is covered by a protective layer forming a sidewall seal. The sensor package also includes a package that encases the light sensor, filter(s) and bond pad(s). Additionally, at least one package pin is communicatively coupled to the bond pad(s). The device also includes a functional circuit that is coupled to the sensor package and receives the sensor information from the light sensor. The device can be an ambient light sensor, camera, backlit mirror, handheld electronic device, filter device, light-to-digital output sensor, gain selection device, proximity sensor, or light-to-voltage non-linear converter.Type: GrantFiled: June 7, 2012Date of Patent: February 24, 2015Assignee: Intersil Americas LLCInventors: Helen Hongwei Li, Joy Ellen Jones, Phillip J. Benzel, Jeanne M. McNamara, John T. Gasner
-
Patent number: 8946912Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: GrantFiled: December 31, 2013Date of Patent: February 3, 2015Assignee: Intersil Americas LLCInventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
-
Publication number: 20140113444Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: ApplicationFiled: December 31, 2013Publication date: April 24, 2014Applicant: INTERSIL AMERICAS INC.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert Lomenick, Chris A. McCarty
-
Patent number: 8652960Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: GrantFiled: December 18, 2012Date of Patent: February 18, 2014Assignee: Intersil Americas Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
-
Patent number: 8569896Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: GrantFiled: June 26, 2012Date of Patent: October 29, 2013Assignee: Intersil Americas Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
-
Patent number: 8536044Abstract: A method for opening a bond pad on a semiconductor device is provided. The method comprises removing a first layer to expose a first portion of the bond pad and forming a protective layer over the exposed first portion of the bond pad. The method further comprises performing subsequent processing of the semiconductor device and removing the protective layer to expose a second portion of the bond pad.Type: GrantFiled: November 30, 2010Date of Patent: September 17, 2013Assignee: Intersil Americas Inc.Inventors: Helen Hongwei Li, Joy Ellen Jones, Phillip J. Benzel, Jeanne M. McNamara, John T. Gasner
-
Patent number: 8338914Abstract: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, a silicide contact junction is formed in the at least one opening to the working surface of the silicon substrate, and interconnect metal layers are formed.Type: GrantFiled: January 19, 2010Date of Patent: December 25, 2012Assignee: Intersil Americas Inc.Inventors: John T. Gasner, John Stanton, Dustin A. Woodbury, James D. Beasom
-
Publication number: 20120261836Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Applicant: INTERSIL AMERICAS INC.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty
-
Publication number: 20120241893Abstract: A device having a detector includes a sensor package. The sensor package includes a light sensor, at least one filter located over the light sensor and at least one bond pad. The light sensor is formed on a semiconductor device that provides sensor information related to light incident upon the light sensor. A perimeter of each bond pad is covered by a protective layer forming a sidewall seal. The sensor package also includes a package that encases the light sensor, filter(s) and bond pad(s). Additionally, at least one package pin is communicatively coupled to the bond pad(s). The device also includes a functional circuit that is coupled to the sensor package and receives the sensor information from the light sensor. The device can be an ambient light sensor, camera, backlit mirror, handheld electronic device, filter device, light-to-digital output sensor, gain selection device, proximity sensor, or light-to-voltage non-linear converter.Type: ApplicationFiled: June 7, 2012Publication date: September 27, 2012Applicant: INTERSIL AMERICAS INC.Inventors: Helen Hongwei Li, Joy Ellen Jones, Phillip J. Benzel, Jeanne M. McNamara, John T. Gasner
-
Patent number: 8274160Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.Type: GrantFiled: June 28, 2010Date of Patent: September 25, 2012Assignee: Intersil Americas Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
-
Publication number: 20120007199Abstract: A method for opening a bond pad on a semiconductor device is provided. The method comprises removing a first layer to expose a first portion of the bond pad and forming a protective layer over the exposed first portion of the bond pad. The method further comprises performing subsequent processing of the semiconductor device and removing the protective layer to expose a second portion of the bond pad.Type: ApplicationFiled: November 30, 2010Publication date: January 12, 2012Applicant: INTERSIL AMERICAS INC.Inventors: Helen Hongwei Li, Joy Ellen Jones, Phillip J. Benzel, Jeanne M. McNamara, John T. Gasner
-
Publication number: 20100261344Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.Type: ApplicationFiled: June 28, 2010Publication date: October 14, 2010Applicant: INTERSIL AMERICAS INC.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty
-
Patent number: 7795130Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.Type: GrantFiled: April 19, 2007Date of Patent: September 14, 2010Assignee: Intersil Americas Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
-
Publication number: 20100117198Abstract: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, a silicide contact junction is formed in the at least one opening to the working surface of the silicon substrate, and interconnect metal layers are formed.Type: ApplicationFiled: January 19, 2010Publication date: May 13, 2010Applicant: INTERSIL AMERICAS INC.Inventors: John T. Gasner, John Stanton, Dustin A. Woodbury, James D. Beasom
-
Patent number: 7662692Abstract: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of the semiconductor device. Cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process including, applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, forming a silicide contact junction in the at least one of the opening to the working surface of the silicon substrate and forming interconnect metal layers.Type: GrantFiled: October 11, 2007Date of Patent: February 16, 2010Assignee: Intersil Americas Inc.Inventors: John T. Gasner, John Stanton, Dustin A. Woodbury, James D. Beasom
-
Patent number: 7341958Abstract: The formation of devices in semiconductor material. In one embodiment, a method of forming a semiconductor device is provided. The method comprises forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of the semiconductor device. Cleaning the semiconductor device with a diluted HF/HCL process. After cleaning with the diluted HF/HCL process, forming a silicide contact junction in the at least one of the opening to the working surface of the silicon substrate and then forming interconnect metal layers.Type: GrantFiled: April 8, 2005Date of Patent: March 11, 2008Assignee: Intersil Americas Inc.Inventors: John T. Gasner, John Stanton, Dustin A. Woodbury, James D. Beasom
-
Patent number: 7224074Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.Type: GrantFiled: December 19, 2005Date of Patent: May 29, 2007Assignee: Intersil Americas Inc.Inventors: John T Gasner, Michael D Church, Sameer D Parab, Paul E Bakeman, Jr., David A Decrosta, Robert Lomenic, Chris A McCarty
-
Patent number: 7005369Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.Type: GrantFiled: October 31, 2003Date of Patent: February 28, 2006Assignee: Intersil American Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty
-
Patent number: 6350640Abstract: To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.Type: GrantFiled: July 18, 1994Date of Patent: February 26, 2002Assignee: Intersil Americas Inc.Inventors: Robert T. Fuller, Chris McCarty, John T. Gasner, Michael D. Church
-
Patent number: 5808348Abstract: A semiconductor device which includes a polysilicon gate separated from a semiconductor substrate by a re-oxidized nitrided oxide film in which the concentration of re-oxidized nitride in the film underlying the gate is non-uniform and in which the concentration of nitrogen in the substrate and the re-oxidized nitrided oxide along their interface and underlying the gate is non-uniform.Methods are disclosed of providing the non-uniform concentrations by incomplete shielding of the oxide by the gate during the nitriding and re-oxidizing process.Type: GrantFiled: June 27, 1997Date of Patent: September 15, 1998Assignee: Harris CorporationInventors: Akira Ito, John T. Gasner