Abstract: Room temperature-testing of an MOS field effect transistor architecture, whose parameters have been optimized for operation at cryogenic temperatures, is facilitated by applying a prescribed reverse body-to-source voltage bias, that modifies the variation of the drain-to-source current vs. gate-to-source voltage characteristic, so as to shift the gate threshold voltage to a value corresponding to the device operating at its optimally designed cryogenic temperature. The magnitude of this back bias voltage is set at a value which adds to the number of charges required to balance the gate voltage before an inversion condition is achieved. In effect, the back bias causes the depletion layer beneath the gate to be expanded into the body beneath the gate, thereby compensating for what would otherwise be depletion mode operation, if the cryogenically designed MOS device were placed at room temperature.

Abstract: A method of making a semiconductor device in which a polysilicon gate is separated from a semiconductor substrate by a re-oxidized nitrided oxide film and in which the concentration of re-oxidized nitride in the film underlying the gate is non-uniform. The concentration of nitrogen in the substrate and the re-oxidized nitrided oxide along their interface and underlying the gate is non-uniform. The non-uniform concentrations are provided by incomplete shielding of the oxide by the gate during the nitriding and re-oxidizing processes.

Abstract: An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.

Abstract: In a method of etching a thin film resistor material, such as NiCr or CrSi, and of producing a thin film resistor, a non-photoresist hard mask is deposited on an exposed surface of thin film resistor material, a delineated portion of the hard mask is etched with a hydrogen peroxide etchant that does not affect the thin film resistor material to expose the material therebeneath, and the exposed thin film resistor material is etched with a second etchant that does not affect the hard mask. The second etchant may be sulfuric acid heated to greater than 125.degree. C. for NiCr or a mixture of phosphoric acid, nitric acid and hydrofluoric acid for CrSi. The hard mask preferably comprises TiW.

Abstract: A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Abstract: A protection circuit including complementary bipolar transistors having collectors connected to an input and base and emitters connected together to a respective voltage source. The bipolar transistors are lateral transistors having a field plate over the base region and spaced laterally from the laterally spaced collector and emitter regions. The base may include increased impurity surface regions extending from the emitter and collector to the gate to increase the beta and decrease the collector-base breakdown.

Abstract: A method is provided for semiconductor manufacture wherein a via is defined and etched through an insulative layer of the device to an underlying conductive region and metal fillets are formed in the corner regions of the via. A conformal metal layer is then deposited onto the device and etched until all metal is removed from the insulative layer surface. Finally, a second metal interconnect layer is deposited onto the device and the desired interconnect pattern is defined. The fillets displace the metal subsequently deposited on the via side surface laterally toward the center of the via, thereby preventing severe self-shadowing problems and improving step coverage of metal into the via.

Abstract: CMOS devices are formed in self-aligned wells in a substrate produced by a two mask, one photolithographic step process wherein the first mask is used as a template to form the second inverse mask of substantially equal thickness. The gates are used as alignment mask for shallow source and drain regions and subsequently formed lateral gate spacers are used as alignment mask for deep source and drain regions. Exposed source and drain regions and silicon gates have silicide formed thereon by a non-selective process.

Abstract: A reverse mask is formed after the first ion implantation step by applying a second masking material to at least fill the opening in the first mask layer and removing the second mask material to reveal at least a portion of the first mask layer. The first mask layer is then selectively removed with any superimposed second mask layer material thereon. This forms a truly inverse mask. Second conductivity impurities are then introduced through the inverse mask to form self-aligned complementary wells in a substrate.

Abstract: Complementary MOS devices having spaced guard rings are fabricated by applying an oxide layer to an N substrate with an opening for doping P-type impurities to form a well, applying a nitride layer over a portion of the oxide and of the well portions, doping the area in the well between the nitride and the oxide to form P-type guard rings, masking the well and adjacent portion of the oxide, doping the area between the mask and the exposed nitride layer to form N-type guard rings and exposing the substrate to an oxidizing atmosphere to oxidize the substrate except where covered by the nitride layer. The nitride layer is removed and standard device processing is used to form complementary MOS in the areas previously covered by the nitride.

Abstract: Complementary MOS devices having spaced guard rings are fabricated by applying an oxide layer to an N substrate with an opening for doping P-type impurities to form a well, applying a nitride layer over a portion of the oxide and of the well portions, doping the area in the well between the nitride and the oxide to form P-type guard rings, masking the well and adjacent portion of the oxide, doping the area between the mask and the exposed nitride layer to form N-type guard rings and exposing the substrate to an oxidizing atmosphere to oxidize the substrate except where covered by the nitride layer. The nitride layer is removed and standard device processing is used to form complementary MOS in the areas previously covered by the nitride.