Abstract: A method and apparatus for forming a super-lattice structure on a substrate is described herein. The super-lattice structure includes a plurality of silicon-germanium layers and a plurality of silicon layers disposed in a stacked pattern. The methods described herein produce a super-lattice structure with transition width of less than about 1.4 nm between each of the silicon-germanium layers and an adjacent silicon layer. The methods described herein include flowing one or a combination of a silicon containing gas, a germanium containing gas, and a halogenated species.

Abstract: Embodiments of the present disclosure generally relate to the field of semiconductor manufacturing processes, more particularly, to precursor chemistries and methods of depositing silicon-containing films for forming semiconductor devices. In one or more embodiments, a method includes co-flowing a silicon-containing precursor with a dopant precursor into a processing chamber at a temperature of 600° C. or less to deposit an epitaxial layer over a substrate disposed within the processing chamber. The silicon-containing precursor is selected from a list consisting of silane (SiH4), disilane (Si2H6), trisilane(Si3H8), tetrasilane (Si4H10), monochlorotrisilane (Si3H7Cl), diiodosilane (SiH2I2), and dibromosilane (SiH2Br2).

Abstract: A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-clean process on exposed surfaces of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surfaces of the semiconductor structure, (c) a recrystallization anneal process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench, (d) an etch process to remove remaining portions of the amorphous silicon-containing layer, and (e) a second deposition process, to epitaxially form a source/drain region over the silicon-containing crystalline layer wi

Abstract: Methods and systems for fabricating semiconductor devices that use a cyclic pulse-etch-purge process, particularly after epitaxial film deposition, are provided. The process involves alternating flows of etch and purge gases (such as H2, N2, HCl, Cl2, and others) and optionally deposition gases to selectively remove unwanted doped silicon-containing material, shaping epitaxial features with precise profiles and minimizing defects like voids. The method can be performed in-situ in the same chamber as deposition and uses controlled cycles of gas pulses to achieve targeted source/drain feature formation. It supports various process parameters and chemistries, is compatible with standard nMOS and pMOS conditions, and can be implemented in automated semiconductor manufacturing environments.

Abstract: Systems and methods for manufacturing semiconductor devices, specifically focusing on cyclic epitaxial growth and etching within a semiconductor structure are provided. The method includes forming a source and drain material on a structure of a substrate and etching the source and drain material. The etching is conducted in a plurality of etch cycles that respectively include flowing a purge gas and flowing an etch gas to etch the source and drain material. The source and drain material can be an n-type doped silicon-containing layer formed using a dopant source including an organophosphine. This cycle is repeated to achieve the targeted thickness. The process enhances the quality and performance of multi-gate devices like gate-all-around transistors by reducing defects and improving uniformity.

Abstract: Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude.

Abstract: Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude.

Abstract: A susceptor for processing a substrate is provided including a base and a coating formed over the base. The base includes an outer rim having an inner edge, an outer edge, and a top connecting the inner edge to the outer edge; and an inner dish disposed inside the outer rim and coupled to the outer rim, the inner dish recessed from the top of the outer rim, the inner dish having a front side and an opposing back side. The coating has an outer surface that includes a first portion formed over the front side of the inner dish. The first portion of the outer surface of the coating includes a first region and a second region, the first region has a first average level of roughness, the second region has a second average level of roughness.

Abstract: Superlattice structures that may be used in gate-all around (GAA) transistor devices and methods for manufacturing the same are provided. In one or more implementations of the present disclosure, carbon-containing precursors are used to dose the SiGe surface prior to silicon channel growth to suppress germanium diffusion. The carbon-containing precursors can be selected from organosilane precursors, organogermane precursors, and carbon precursors. The carbon-containing precursor can be used with chlorinated precursors. The carbon-containing precursor can be flowed throughout the growth of the entire SiGe thickness. The carbon-containing precursor can be flowed toward the end of the growth of the SiGe thickness. The carbon-containing precursor can be flowed after growth of the SiGe thickness.

Abstract: The present disclosure relates to UV light sources and/or processing activation in processing chambers, and related apparatus and methods. In one or more embodiments, a processing chamber applicable for semiconductor manufacturing includes a chamber body and a lid. The lid and the chamber body at least partially define an internal volume. The processing chamber further includes a substrate support disposed in a processing volume of the internal volume and a gas inlet fluidly coupled to the chamber body to provide gas to the internal volume. The gas inlet includes one or more UV energy sources for irradiating gas within the inlet prior to the gas entering the processing volume. The one or more UV energy sources comprise a first UV energy source having a first peak wavelength and second UV energy source having a second peak wavelength different from the first wavelength.

Abstract: The present disclosure provides systems and methods of processing substrates. A surface of a substrate is exposed to an inhibitor. The surface of the substrate includes one or more dielectric regions and one or more semiconductor regions. The inhibitor includes a halogen-containing compound including tin. A silicon-containing material layer is epitaxially and selectively deposited on the substrate after exposing the surface of the substrate to the inhibitor.

Abstract: The present disclosure relates to flow guide structures and heat shield structures, and related methods, for deposition uniformity and process adjustability. In one implementation, an apparatus for substrate processing includes a chamber body that includes a processing volume. The apparatus includes one or more heat sources. The apparatus includes a flow guide structure positioned in the processing volume. The flow guide structure includes one or more first flow dividers that divide the processing volume into a plurality of flow levels, and one or more second flow dividers oriented to intersect the one or more first flow dividers and divide each flow level of the plurality of flow levels into a plurality of flow sections. The flow guide structure includes one or more third flow dividers oriented to intersect the one or more second flow dividers and divide the plurality of flow sections into a plurality of flow zones.

Abstract: Methods and devices for epitaxially growing boron- and gallium-doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

Abstract: Methods and devices for epitaxially growing boron- and gallium-doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

Abstract: A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA metalorganic dopant precursor. The methods may further include depositing a Group IV semiconductor on a surface of the substrate. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Abstract: Gas-phase reactor systems and methods suitable for use with precursors that are solid phase at room temperature and pressure are disclosed. The systems and methods as described herein can be used to, for example, form amorphous, polycrystalline, or epitaxial layers (e.g., one or more doped semiconductor layers) on a surface of a substrate.

Abstract: A method of cleaning an epitaxial reaction chamber in-situ is disclosed. The method may include a pre-coating step, a high temperature baking step, and a gas etching step. The method is able to remove residue buildup within the reaction chamber, which may be made of quartz.

Abstract: Exemplary semiconductor processing methods may include performing a pre-treatment on a substrate housed within a processing region of a semiconductor processing chamber. The substrate may include a layer of silicon-and-carbon-containing material. The pre-treatment may remove native oxide or residue from a surface of the layer of silicon-and-carbon-containing material. The methods may include providing a silicon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the silicon-containing precursor. The contacting may deposit a layer of silicon-containing material on the layer of silicon-and-carbon-containing material. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the oxygen-containing precursor.