Abstract: A method of creating an electrical connection involves providing a pair of contacts each on one of two different chips, the pair of contacts defining a volume therebetween, the volume containing at least two compositions each having melting points, the compositions having been selected such that heating to a first temperature will cause a change in at least one of the at least two compositions such that the change will result in a new composition having a new composition melting point of a second temperature, greater than the first temperature and the melting point of at least a first of the at least two compositions, and heating the pair of contacts and the at least two compositions to the first temperature.

Abstract: A method of creating an electrical contact involves locating a barrier material at a location for an electrical connection, providing an electrically conductive bonding metal on the barrier material, the electrically conductive bonding metal having a diffusive mobile component, the volume of barrier material and volume of diffusive mobile component being selected such that the barrier material volume is at least 20% of the volume of the combination of the barrier material volume and diffusive mobile component volume. An electrical connection has an electrically conductive bonding metal between two contacts, a barrier material to at least one side of the electrically conductive bonding metal, and an alloy, located at an interface between the barrier material and the electrically conductive bonding metal. The alloy includes at least some of the barrier material, at least some of the bonding metal, and a mobile material.

Abstract: A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane.

Abstract: A method involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package.

Abstract: A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above the seed layer that is at least equal to a thickness of the seed layer, removing the solid photoresist, and removing seed layer exposed by removal of the photoresist and plated metal until all of the exposed seed layer has been removed.

Abstract: A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver.

Abstract: An electrically conductive interconnect system has a post, extending above a supporting surface, the post including a rigid material, a coating on the rigid material, wherein the post and has a first width at the supporting surface and a second width at a distance removed from the supporting surface, and the post narrows from the first width to the second width. A method of electrically connecting a portion of a first supporting surface to a portion of a second supporting surface involves bringing a post on the first supporting surface into contact with an electrically conductive material located on the second supporting surface, softening the electrically conductive material, causing a separation distance between the first supporting surface and the second supporting distance to decrease so that a portion of the post will be surrounded by the electrically conductive material, and allowing the temperature of the electrically conductive material to decrease.

Abstract: A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 ?m. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 ?m.

Abstract: A method of electrically conductive via formation in a fully processed wafer involves defining at least one trench area on a backside of the fully processed wafer, forming at least one trench within the trench area to an overall depth that will allow for a via formed within the trench to be seeded over its full length, forming the via within the trench into the fully processed wafer to a predetermined depth, depositing a seed layer over the full length of the via, and plating the seed layer to fill the via with an electrically conductive metal.

Abstract: A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs.

Abstract: A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metallization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.

Abstract: A method involves forming vias in a blank semiconductor wafer, making at least some of the vias in the blank semiconductor wafer electrically conductive, and performing front end processing on the blank wafer so as to create devices on the wafer that are connected to the electrically conductive vias.

Abstract: A detector is disposed on the passive side of a laser to detect photon leakage through the passive side mirror and measure as current created in the detector via a Schottky contact.

Abstract: An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area.

Abstract: A system has multiple discrete functional system subcomponents which, when interconnected form the system, each of the subcomponents being on a discrete substrate and being electrically interconnected to at least one of the other subcomponents by a through-chip via. A method of creating a system involves creating multiple discrete chips, each including at least one system subcomponent, forming electrically conductive vias in at least some of the chips such that some of the chips can be electrically connected to others of the chips, arranging the chips such that: some are coplanar in a first plane, at least one other lies in a second plane parallel to those in the first plane, and at least one of the chips in the first plane is connected to at least one of the chips in the second plane; and electrically interconnecting corresponding chips of the multiple discrete chips using the vias.

Abstract: An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.

Abstract: A method of electrically joining a first contact on a first wafer with a second contact on a second wafer, the first contact, a rigid material, and the second contact, a material that is malleable relative to the rigid material, such that when brought together the rigid material will penetrate the malleable material, the rigid and malleable materials both being electrically conductive involves bringing the rigid material into contact with the malleable material, applying a force to one of the first contact or the second contact so as to cause the rigid material to penetrate the malleable material, heating the rigid and malleable material so as to cause the malleable material to soften, and constraining the malleable material to within a pre-specified area.

Abstract: A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

Abstract: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.

Abstract: A chip has a wafer portion of a first coefficient of thermal expansion, the wafer portion including at least one via defined by a peripheral sidewall, an insulating region having second average coefficient of thermal expansion, located within the via and covering at least a portion of the peripheral sidewall to a first thickness, a metallic region having a third average coefficient of thermal expansion, located within the via and covering the insulator to a second thickness, the first thickness and second thickness being selected such that expansion of the combination of the insulator and the metal due to heat will match the expansion of the wafer portion as a result of the combined effect of the first and second thicknesses and their respective second and third average coefficients of thermal expansion.