Patents by Inventor John Twynam
John Twynam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929405Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.Type: GrantFiled: April 13, 2021Date of Patent: March 12, 2024Assignee: Infineon Technologies AGInventors: Albert Birner, Helmut Brech, John Twynam
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Patent number: 11869963Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.Type: GrantFiled: April 29, 2022Date of Patent: January 9, 2024Assignee: Infineon Technologies AGInventors: John Twynam, Albert Birner, Helmut Brech
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Publication number: 20230170393Abstract: A Group III nitride-based transistor device is provided that has a gate drain capacitance (CGD), a drain source capacitance (CDS) and a drain source on resistance (RDSon). A ratio of the gate drain capacitance (CGD) at a drain source voltage (VDS) of 0V, CGD (0V), and the gate drain capacitance CGD at a value of VDS>0V, CGDV, is at least 3:1, wherein VDS is less than 15V.Type: ApplicationFiled: April 28, 2021Publication date: June 1, 2023Inventors: Helmut Brech, John Twynam
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Publication number: 20230155000Abstract: A method includes providing a semiconductor body, forming a thermosensitive element on or within the semiconductor body, forming a structured laser-reflective mask on the upper surface of the semiconductor body that covers the thermosensitive element and includes first and second openings, and performing a laser thermal annealing process that transmits laser energy through the first and second openings and into the semiconductor body, wherein the thermosensitive element comprises a critical temperature at which the thermosensitive element is irreparably damaged, wherein the laser thermal annealing process brings portions of the semiconductor body that are underneath the first and second openings to above the critical temperature, and wherein during the laser thermal annealing process the thermosensitive element remains below the critical temperature.Type: ApplicationFiled: January 5, 2023Publication date: May 18, 2023Inventors: Albert Birner, Rudolf Berger, Helmut Brech, Olaf Storbeck, Haifeng Sun, John Twynam
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Patent number: 11581418Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.Type: GrantFiled: June 5, 2020Date of Patent: February 14, 2023Assignee: Infineon Technologies AGInventors: Albert Birner, Rudolf Berger, Helmut Brech, Olaf Storbeck, Haifeng Sun, John Twynam
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Publication number: 20220254913Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.Type: ApplicationFiled: April 29, 2022Publication date: August 11, 2022Inventors: John Twynam, Albert Birner, Helmut Brech
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Patent number: 11342451Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.Type: GrantFiled: November 27, 2019Date of Patent: May 24, 2022Assignee: Infineon Technologies AGInventors: John Twynam, Albert Birner, Helmut Brech
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Publication number: 20210384318Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.Type: ApplicationFiled: June 5, 2020Publication date: December 9, 2021Inventors: Albert Birner, Rudolf Berger, Helmut Brech, Olaf Storbeck, Haifeng Sun, John Twynam
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Publication number: 20210336043Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.Type: ApplicationFiled: April 22, 2021Publication date: October 28, 2021Inventors: Albert Birner, Helmut Brech, John Twynam
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Publication number: 20210336015Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.Type: ApplicationFiled: April 13, 2021Publication date: October 28, 2021Inventors: Albert Birner, Helmut Brech, John Twynam
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Publication number: 20210226039Abstract: In an embodiment, a method for fabricating a semiconductor wafer includes: epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness tw, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface; removing portions of the III-V semiconductor to produce a plurality of mesas including the III-V semiconductor arranged on the first surface of the wafer; applying an insulation layer to regions of the wafer arranged between the mesas; and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.Type: ApplicationFiled: January 11, 2021Publication date: July 22, 2021Inventors: Helmut Brech, Albert Birner, John Twynam
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Publication number: 20200395447Abstract: In an embodiment, a semiconductor device includes a support layer having a first surface configured to support epitaxial growth of at least one Group III nitride, an epitaxial Group III nitride-based multi-layer structure positioned on the first surface of the support layer, and a parasitic channel suppression region positioned at the first surface of the support layer.Type: ApplicationFiled: June 16, 2020Publication date: December 17, 2020Inventors: Helmut Brech, Albert Birner, John Twynam
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Publication number: 20200176594Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.Type: ApplicationFiled: November 27, 2019Publication date: June 4, 2020Inventors: John Twynam, Albert Birner, Helmut Brech
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Patent number: 10403723Abstract: A semiconductor device is disclosed. The semiconductor device includes a second conductive type substrate including a first first-conductive-type doping layer and a plurality of devices on the second conductive type substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the first first-conductive-type doping layer, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the first first-conductive-type doping layer and the first nitride semiconductor layer, a first contact electrically connected to the first heterojunction interface, and a contact connector electrically connecting the first contact to the first first-conductive-type doping layer.Type: GrantFiled: January 17, 2014Date of Patent: September 3, 2019Assignee: LG Innotek Co., Ltd.Inventor: John Twynam
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Patent number: 9825026Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a plurality of devices on the substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the substrate and the first nitride semiconductor layer, a third nitride semiconductor layer brought together with the second nitride semiconductor layer to form a second heterojunction interface, between the substrate and the second nitride semiconductor layer, and a first contact electrically connected to the first and second heterojunction interfaces.Type: GrantFiled: January 17, 2014Date of Patent: November 21, 2017Assignee: LG INNOTEK., LTD.Inventor: John Twynam
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Publication number: 20170005086Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a plurality of devices on the substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the substrate and the first nitride semiconductor layer, a third nitride semiconductor layer brought together with the second nitride semiconductor layer to form a second heterojunction interface, between the substrate and the second nitride semiconductor layer, and a first contact electrically connected to the first and second heterojunction interfaces.Type: ApplicationFiled: January 17, 2014Publication date: January 5, 2017Inventor: John TWYNAM
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Publication number: 20160372555Abstract: A semiconductor device is disclosed. The semiconductor device includes a second conductive type substrate including a first first-conductive-type doping layer and a plurality of devices on the second conductive type substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the first first-conductive-type doping layer, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the first first-conductive-type doping layer and the first nitride semiconductor layer, a first contact electrically connected to the first heterojunction interface, and a contact connector electrically connecting the first contact to the first first-conductive-type doping layer.Type: ApplicationFiled: January 17, 2014Publication date: December 22, 2016Inventor: John TWYNAM
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Patent number: 8017977Abstract: A GaN heterojunction FET has an AlxGa1-xN first graded layer and an AlyGa1-yN second graded layer, which are formed sequentially on a channel layer. The Al mole fraction x of the first graded layer decreases linearly from, for example, 0.2 at an interface of the first graded layer with the channel layer to 0.1 at an interface thereof with the second graded layer. The Al mole fraction y of the second graded layer increases from, for example, 0.1 at an interface of the second graded layer with the first graded layer to 0.35 at a surface located on the opposite side from the first graded layer. Because the intrinsic polarization of AlGaN depends on the Al mole fraction, fixed negative charge is generated in the AlxGa1-xN first graded layer, and fixed positive charge is generated in the AlyGa1-yN second graded layer.Type: GrantFiled: November 14, 2007Date of Patent: September 13, 2011Assignee: Sharp Kabushiki KaishaInventor: John Twynam
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Patent number: 7629632Abstract: In a heterostructure field effect transistor (MISHFET), a source ohmic electrode 105 and a drain ohmic electrode 106 are formed on an AlGaN barrier layer 104. A SiNx gate insulator 108, a p-type polycrystalline SiC layer 109, and a Pt/Au gate electrode 110 being an ohmic electrode are formed one on another on the AlGaN barrier layer 104. Since the p-type polycrystalline SiC layer 109 is relatively large in work function, the channel of the MISHFET is depleted even in its zero-bias state, so that the normally-OFF operation occurs.Type: GrantFiled: October 31, 2007Date of Patent: December 8, 2009Assignee: Sharp Kabushiki KaishaInventor: John Twynam
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Patent number: 7538364Abstract: On a substrate of a GaN FET, an undoped AlN layer, a GaN delta doped layer, an undoped GaN layer, and an undoped Al0.2Ga0.8N layer are formed in sequence. Arranged on the undoped Al0.2Ga0.8N layer are a Ti/Al/Pt/Au source ohmic electrode, a Pt/Au gate Schottky electrode, and a Ti/Al/Pt/Au drain ohmic electrode. Parallel conduction and gate leak are reduced or eliminated by the GaN delta doped layer.Type: GrantFiled: January 23, 2004Date of Patent: May 26, 2009Assignee: Sharp Kabushiki KaishaInventor: John Twynam