Patents by Inventor John Twynam

John Twynam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080308843
    Abstract: A GaN heterojunction FET has an AlxGa1-xN first graded layer and an AlyGa1-yN second graded layer, which are formed sequentially on a channel layer. The Al mole fraction x of the first graded layer decreases linearly from, for example, 0.2 at an interface of the first graded layer with the channel layer to 0.1 at an interface thereof with the second graded layer. The Al mole fraction y of the second graded layer increases from, for example, 0.1 at an interface of the second graded layer with the first graded layer to 0.35 at a surface located on the opposite side from the first graded layer. Because the intrinsic polarization of AlGaN depends on the Al mole fraction, fixed negative charge is generated in the AlxGa1-xN first graded layer, and fixed positive charge is generated in the AlyGa1-yN second graded layer.
    Type: Application
    Filed: November 14, 2007
    Publication date: December 18, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: John Twynam
  • Publication number: 20080210988
    Abstract: In a heterostructure field effect transistor (MISHFET), a source ohmic electrode 105 and a drain ohmic electrode 106 are formed on an AlGaN barrier layer 104. A SiNx gate insulator 108, a p-type polycrystalline SiC layer 109, and a Pt/Au gate electrode 110 being an ohmic electrode are formed one on another on the AlGaN barrier layer 104. Since the p-type polycrystalline SiC layer 109 is relatively large in work function, the channel of the MISHFET is depleted even in its zero-bias state, so that the normally-OFF operation occurs.
    Type: Application
    Filed: October 31, 2007
    Publication date: September 4, 2008
    Inventor: John Twynam
  • Publication number: 20080105902
    Abstract: In the rectifier, a barrier layer and a channel layer constitute a heterojunction portion, and a two-dimensional electron gas channel is generated in the vicinity of a boundary between the channel layer and the barrier layer. A Schottky gate electrode is connected to an anode ohmic electrode and extends from above the anode ohmic electrode over to the barrier layer and a recess formed in the barrier layer is covered with the Schottky gate electrode. The two-dimensional electron gas channel located just below the recess is depleted by the influence of the Schottky gate electrode in a state in which there is no application voltage. By virtue of the formation of the recess in the barrier layer, the threshold voltage at which electrons are generated in the two-dimensional electron gas channel located just below the gate electrode is lowered, and the rise voltage can be made lower than that of the conventional Schottky diode.
    Type: Application
    Filed: October 24, 2007
    Publication date: May 8, 2008
    Inventor: John Twynam
  • Publication number: 20070152239
    Abstract: A semiconductor device has a semiconductor layer, and a first electrode (Schottky electrode or MIS electrode) and a second electrode (ohmic electrode) which are formed on the semiconductor layer apart from each other. The first electrode has a cross section in the shape of a polygon. A second electrode-side corner of the polygon has an interior angle of which an outward extension line of a bisector crosses the semiconductor layer or the second electrode. The interior angle of such a second electrode-side corner is larger than 90°.
    Type: Application
    Filed: November 30, 2006
    Publication date: July 5, 2007
    Inventors: Masaharu Yamashita, John Twynam
  • Publication number: 20070102727
    Abstract: A field-effect transistor in the present invention has a source, a first gate, a second gate and a drain, which are formed in this order at positions away from each other on a semiconductor layer along the surface of the semiconductor layer and each of which has a metal electrode. The first gate has normally-off structure, while the second gate has normally-on structure. The first gate is of Schottky type, while the second gate is of MIS type.
    Type: Application
    Filed: November 1, 2006
    Publication date: May 10, 2007
    Applicant: Sharp Kabushiki Kaisha
    Inventor: John Twynam
  • Publication number: 20060065911
    Abstract: In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the active layer. A dielectric layer (TiO2 layer) of a stepwise laminate structure is formed on the AlGaN layer so that the electric field distribution between the gate Schottky electrode and the drain ohmic electrode is substantially uniformed. The dielectric constant of TiO2 of the dielectric layer is made higher than the dielectric constant of GaN and AlGaN of the active layer.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 30, 2006
    Inventor: John Twynam
  • Publication number: 20050227638
    Abstract: An input modulation signal wave 108a is frequency-upconverted to an intermediate frequency signal wave by a frequency mixer 3. By adding a reference signal wave to the intermediate frequency signal wave frequency-upconverted by the frequency mixer 3 by means of a signal combiner 5a, an intermediate frequency multiplex signal wave 7 is generated. The intermediate frequency multiplex signal wave 7 is frequency-upconverted to a milliwave by a second frequency mixer 8. The multiplex signal wave in the milliwave band frequency-upconverted by the second frequency mixer 8 is amplified by a transmission amplifier 10 and transmitted as a radio multiplex signal wave 115 constituted of a radio reference signal wave 106 and a radio signal wave 107 from a transmission antenna 15.
    Type: Application
    Filed: February 25, 2003
    Publication date: October 13, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Eiji Suematsu, John Twynam
  • Publication number: 20050116319
    Abstract: A bipolar transistor of the present invention comprises a collector layer made of an n-type semiconductor and an emitter layer made of an n-type semiconductor provided on this collector layer. A gate layer for injecting p-type carriers (holes) into the emitter layer is provided on the emitter layer. A p-type carrier retaining layer is formed between the collector layer and the emitter layer. The p-type carrier retaining layer temporarily retains the p-type carriers that are injected from the gate layer into the emitter layer and diffused in the emitter layer and reach the p-type carrier retaining layer. The bipolar transistor has a structure whose performance is not influenced by sheet resistance of the base layer, and is able to exhibit a high current gain even in a high-frequency region.
    Type: Application
    Filed: November 24, 2004
    Publication date: June 2, 2005
    Inventor: John Twynam
  • Publication number: 20040211976
    Abstract: On a substrate of a GaN FET, an undoped AlN layer, a GaN delta doped layer, an undoped GaN layer, and an undoped Al0.2Ga0.8N layer are formed in sequence. Arranged on the undoped Al0.2Ga0.8N layer are a Ti/Al/Pt/Au source ohmic electrode, a Pt/Au gate Schottky electrode, and a Ti/Al/Pt/Au drain ohmic electrode. Parallel conduction and gate leak are reduced or eliminated by the GaN delta doped layer.
    Type: Application
    Filed: January 23, 2004
    Publication date: October 28, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: John Twynam