Patents by Inventor John V. Veliadis

John V. Veliadis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8130023
    Abstract: A system and method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. Embodiments include a first vertical-channel junction gate field-effect transistor (VJFET), a second VJFET, a gate drive coupled to the first VJFET gate and the second VJFET gate. Both VJFETs include a gate, drain (D1 and D2), and a source, and have gate-to-drain and gate-to-source built-in potentials. The first VJFET and the second VJFET are connected back-to-back in series so that the sources of each are shorted together at a common point S. The gate drive applies an equal voltage bias (VG) to both the gates. The gate drive is configured to selectively bias VG so that current flows through the VJFETs in the D1 to D2 direction, flows through the VJFETs in the D2 to D1 direction or voltages applied to D1 of the first VJFET or D2 of the second VJFET are blocked.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8110880
    Abstract: Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method that includes depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a single lithography step to pattern a mask over the interconnect metallization material, etching the interconnect metallization material in non-masked areas, and removing the stop-etch layer. A system comprises a stop-etch layer material for deposit into a stop-etch layer over a wafer, an interconnect metallization material for deposit over the chrome layer, a lithography operation for patterning a mask over the interconnect metallization material, a first etching compound for etching the interconnect metallization material, where the etching stops at the stop-etch layer, and a second etching compound for removing the stop-etch layer.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: February 7, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8110494
    Abstract: Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: February 7, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventors: John V. Veliadis, Eric Jonathan Stewart, Megan Jean McCoy, Li-shu Chen, Ty Richard McNutt
  • Patent number: 8106422
    Abstract: An avalanche photodiode semiconductor device (20) for converting an impinging photon (22) includes a base n+ doped material layer (52) formed having a window section (72) for passing the photon (22). An n? doped material layer (30) is formed on the n+ doped material layer (52) having a portion of a lower surface (74) suitably exposed. An n+ doped material layer (32) is formed on the n? doped material (30). A p+ layer (24) formed on top of the n+ doped layer (32). At least one guard ring (26) is formed in the n? doped layer (30).
    Type: Grant
    Filed: October 16, 2010
    Date of Patent: January 31, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8105911
    Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: January 31, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20110121883
    Abstract: A system and method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. Embodiments include a first vertical-channel junction gate field-effect transistor (VJFET), a second VJFET, a gate drive coupled to the first VJFET gate and the second VJFET gate. Both VJFETs include a gate, drain (D1 and D2), and a source, and have gate-to-drain and gate-to-source built-in potentials. The first VJFET and the second VJFET are connected back-to-back in series so that the sources of each are shorted together at a common point S. The gate drive applies an equal voltage bias (VG) to both the gates. The gate drive is configured to selectively bias VG so that current flows through the VJFETs in the D1 to D2 direction, flows through the VJFETs in the D2 to D1 direction or voltages applied to D1 of the first VJFET or D2 of the second VJFET are blocked.
    Type: Application
    Filed: November 23, 2009
    Publication date: May 26, 2011
    Applicant: Northrop Grumman Systems Corporation
    Inventor: John V. VELIADIS
  • Publication number: 20110024768
    Abstract: An avalanche photodiode semiconductor device (20) for converting an impinging photon (22) includes a base n+ doped material layer (52) formed having a window section (72) for passing the photon (22). An n? doped material layer (30) is formed on the n+ doped material layer (52) having a portion of a lower surface (74) suitably exposed. An n+ doped material layer (32) is formed on the n? doped material (30). A p+ layer (24) formed on top of the n+ doped layer (32). At least one guard ring (26) is formed in the n? doped layer (30).
    Type: Application
    Filed: October 16, 2010
    Publication date: February 3, 2011
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: John V. Veliadis
  • Patent number: 7863647
    Abstract: An avalanche photodiode semiconductor device (20) for converting an impinging photon (22) includes a base n+ doped material layer (52) formed having a window section (72) for passing the photon (22). An n? doped material layer (30) is formed on the n+ doped material layer (52) having a portion of a lower surface (74) suitably exposed. An n+ doped material layer (32) is formed on the n? doped material (30). A p+ layer (24) formed on top of the n+ doped layer (32). At least one guard ring (26) is formed in the n? doped layer (30).
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: January 4, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20100264427
    Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.
    Type: Application
    Filed: July 1, 2010
    Publication date: October 21, 2010
    Applicant: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 7667242
    Abstract: Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 23, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: John V. Veliadis, Eric Jonathan Stewart, Megan Jean McCoy, Li-Shu Chen, Ty Richard McNutt
  • Patent number: 7557046
    Abstract: Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method comprises depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a single lithography step to pattern a mask over the interconnect metallization material, etching the interconnect metallization material in non-masked areas, and removing the stop-etch layer. A system comprises means for depositing the stop-etch layer over a wafer, means for depositing an interconnected metallization layer over the chrome layer, means for patterning a mask over the interconnect metallization layer, means for etching the interconnect metallization layer, where the etching stops at the stop-etch layer, and means for removing the stop-etch layer.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: July 7, 2009
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis