Patents by Inventor John Vannortwick
John Vannortwick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7476277Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.Type: GrantFiled: November 4, 2003Date of Patent: January 13, 2009Assignee: Micron Technology, Inc.Inventors: Tongbi Jiang, Chad A. Cobbley, John VanNortwick
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Patent number: 7105366Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: September 8, 2005Date of Patent: September 12, 2006Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 7074648Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: November 14, 2003Date of Patent: July 11, 2006Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 7005878Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: July 27, 2004Date of Patent: February 28, 2006Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 6982177Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: July 27, 2004Date of Patent: January 3, 2006Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 6972200Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is eliminated.Type: GrantFiled: October 23, 2003Date of Patent: December 6, 2005Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 6967113Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: November 24, 2003Date of Patent: November 22, 2005Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 6962826Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: July 27, 2004Date of Patent: November 8, 2005Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 6953700Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: August 25, 2004Date of Patent: October 11, 2005Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 6954081Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: January 8, 2003Date of Patent: October 11, 2005Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 6953699Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: July 27, 2004Date of Patent: October 11, 2005Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 6949943Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: GrantFiled: July 27, 2004Date of Patent: September 27, 2005Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Publication number: 20050145169Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.Type: ApplicationFiled: July 29, 2003Publication date: July 7, 2005Inventors: Tongbi Jiang, Chad Cobbley, John VanNortwick
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Publication number: 20050024080Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: ApplicationFiled: August 25, 2004Publication date: February 3, 2005Inventors: Chad Cobbley, John VanNortwick, Bret Street, Tongbi Jiang
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Publication number: 20050007142Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: ApplicationFiled: July 27, 2004Publication date: January 13, 2005Inventors: Chad Cobbley, John VanNortwick, Bret Street, Tongbi Jiang
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Publication number: 20050007141Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: ApplicationFiled: July 27, 2004Publication date: January 13, 2005Inventors: Chad Cobbley, John VanNortwick, Bret Street, Tongbi Jiang
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Publication number: 20040263196Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: ApplicationFiled: July 27, 2004Publication date: December 30, 2004Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Publication number: 20040263197Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: ApplicationFiled: July 27, 2004Publication date: December 30, 2004Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Publication number: 20040263195Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.Type: ApplicationFiled: July 27, 2004Publication date: December 30, 2004Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
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Patent number: 6793749Abstract: Apparatus and method for attaching, assembling, and/or mounting a substrate to any semiconductor device or a flip-chip type semiconductor device.Type: GrantFiled: February 3, 2003Date of Patent: September 21, 2004Assignee: Micron Technology, Inc.Inventors: Rich Fogal, John VanNortwick, Chad A. Cobbley