Patents by Inventor John W. Brothers
John W. Brothers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11423311Abstract: Tuning a neural network may include selecting a portion of a first neural network for modification to increase computational efficiency and generating, using a processor, a second neural network based upon the first neural network by modifying the selected portion of the first neural network while offline.Type: GrantFiled: May 13, 2016Date of Patent: August 23, 2022Inventors: John W. Brothers, Joohoon Lee
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Patent number: 11244225Abstract: Implementing a neural network can include receiving a macro instruction for implementing the neural network within a control unit of a neural network processor. The macro instruction can indicate a first data set, a second data set, a macro operation for the neural network, and a mode of operation for performing the macro operation. The macro operation can be automatically initiated using a processing unit of the neural network processor by applying the second data set to the first data set based on the mode of operation.Type: GrantFiled: June 27, 2016Date of Patent: February 8, 2022Inventors: John W. Brothers, Joohoon Lee
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Publication number: 20210312668Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Inventors: Konstantine Iourcha, John W. Brothers
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Patent number: 11043010Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.Type: GrantFiled: December 10, 2019Date of Patent: June 22, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Konstantine Iourcha, John W. Brothers
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Patent number: 10643339Abstract: An apparatus, system and method is provided to determine a motion of pixels in local regions of a scene, classify the motion into a speed category, and make decisions on how to render blocks of pixels. In one implementation the motion in a tile is classified into at least three different speed regimes. If the pixels in a tile are in a quasi-static speed regime, a determination is made whether or not to reuse a fraction of pixels from the previous frame. If the pixels are determined to be in a high speed regime, a decision is made whether or not a sampling rate may be reduced.Type: GrantFiled: March 6, 2018Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Abhinav Golas, Karthik Ramani, Christopher T. Cheng, John W. Brothers, Liangjun Zhang, Santosh Abraham, Ki Fung Chow
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Publication number: 20200118299Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.Type: ApplicationFiled: December 10, 2019Publication date: April 16, 2020Inventors: Konstantine Iourcha, John W. Brothers
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Patent number: 10510164Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.Type: GrantFiled: June 13, 2016Date of Patent: December 17, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Konstantine Iourcha, John W. Brothers
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Patent number: 10460230Abstract: Reducing computations in a neural network may include determining a group including a plurality of convolution kernels of a convolution stage of a neural network. The convolution kernels of the group are similar to one another. A base convolution kernel for the group may be determined. Scaling factors for a plurality of input feature maps processed by the group may be calculated. The convolution stage of the neural network may be modified to calculate a composite input feature map using the scaling factors and apply the base convolution kernel to the composite input feature map.Type: GrantFiled: February 3, 2016Date of Patent: October 29, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: John W. Brothers, Joohoon Lee
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Patent number: 10417555Abstract: Executing a neural network includes generating an output tile of a first layer of the neural network by processing an input tile to the first layer and storing the output tile of the first layer in an internal memory of a processor. An output tile of a second layer of the neural network can be generated using the processor by processing the output tile of the first layer stored in the internal memory.Type: GrantFiled: May 6, 2016Date of Patent: September 17, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: John W. Brothers, Joohoon Lee
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Patent number: 10387770Abstract: A spiking neural network having a plurality layers partitioned into a plurality of frustums using a first partitioning may be implemented, where each frustum includes one tile of each partitioned layer of the spiking neural network. A first tile of a first layer of the spiking neural network may be read. Using a processor, a first tile of a second layer of the spiking neural network may be generated using the first tile of the first layer while storing intermediate data within an internal memory of the processor. The first tile of the first layer and the first tile of the second layer belong to a same frustum.Type: GrantFiled: March 7, 2016Date of Patent: August 20, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: John W. Brothers, Joohoon Lee
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Patent number: 10089775Abstract: A graphics system interleaves a combination of graphics renderer operations and compute shader operations. A set of API calls is analyzed to determine dependencies and identify candidates for interleaving. A compute shader is adapted to have a tiled access pattern. The interleaving is scheduled to reduce a requirement to access an external memory to perform reads and writes of intermediate data.Type: GrantFiled: December 28, 2015Date of Patent: October 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: John W. Brothers, Joohoon Lee, Abhinav Golas
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Publication number: 20180197304Abstract: An apparatus, system and method is provided to determine a motion of pixels in local regions of a scene, classify the motion into a speed category, and make decisions on how to render blocks of pixels. In one implementation the motion in a tile is classified into at least three different speed regimes. If the pixels in a tile are in a quasi-static speed regime, a determination is made whether or not to reuse a fraction of pixels from the previous frame. If the pixels are determined to be in a high speed regime, a decision is made whether or not a sampling rate may be reduced.Type: ApplicationFiled: March 6, 2018Publication date: July 12, 2018Inventors: Abhinav Golas, Karthik Ramani, Christopher T. Cheng, John W. Brothers, Liangjun Zhang, Santosh Abraham, Ki Fung Chow
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Patent number: 9947071Abstract: A graphics system supports variable rate compression and decompression of texture data and color data. An individual block of data is analyzed to determine a compression data type from a plurality of different compression data types having different compression lengths. The compression data types may include a compression data type for a block having a constant (flat) pixel value over n×n pixels, compression data type in which a subset of 3 or 4 values represents a plane or gradient, and wavelet or other compression type to represent higher frequency content. Additionally, metadata indexing provides information to map between an uncompressed address to a compressed address. To reduce the storage requirement, the metadata indexing permits two or more duplicate data blocks to reference the same piece of compressed data.Type: GrantFiled: June 17, 2015Date of Patent: April 17, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Karthik Ramani, Abhinav Golas, John W. Brothers
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Patent number: 9946331Abstract: Signal processing may include determining a first component common to a first input signal and a second input signal and extracting the first component from at least one of the first input signal or the second input signal, a second component from the first input signal, and a second component from the second input signal. The second component of the first input signal may be different from the second component of the second input signal. An operation may be performed using the extracted, second components. The first component may be combined with a result of the operation.Type: GrantFiled: May 14, 2015Date of Patent: April 17, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Karthik Ramani, Kwontaek Kwon, John W. Brothers
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Patent number: 9928610Abstract: An apparatus, system and method is provided to determine a motion of pixels in local regions of a scene, classify the motion into a speed category, and make decisions on how to render blocks of pixels. In one implementation the motion in a tile is classified into at least three different speed regimes. If the pixels in a tile are in a quasi-static speed regime, a determination is made whether or not to reuse a fraction of pixels from the previous frame. If the pixels are determined to be in a high speed regime, a decision is made whether or not a sampling rate may be reduced.Type: GrantFiled: June 18, 2015Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Abhinav Golas, Karthik Ramani, Christopher T. Cheng, John W. Brothers, Liangjun Zhang, Santosh Abraham, Ki Fung Chow
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Patent number: 9842410Abstract: Image processing may include separating a noise component from an original image resulting in a de-noised image and determining a noise parameterization for the noise component. The de-noised image and the noise parameterization may be compressed.Type: GrantFiled: June 18, 2015Date of Patent: December 12, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: John W. Brothers
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Publication number: 20170344876Abstract: A system and a corresponding method are configured to generate a plurality of output feature maps from an input feature map. The system includes a first input data path (IDP), a request assembly unit (RAU), and a multiply accumulate array (MAA). The IDP transforms a first input feature map to a Winograd domain and generates a first plurality of requests in which each request is for a first plurality of non-zero weights of transformed weight kernels with corresponding elements. The RAU receives the first plurality of requests. The MAA generates a plurality of output matrices in parallel for a first output feature map based on applying the first plurality of non-zero weights to corresponding elements for each input matrix.Type: ApplicationFiled: May 11, 2017Publication date: November 30, 2017Inventor: John W. BROTHERS
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Patent number: 9830714Abstract: In a graphics processing system pixel data and vertex coordinate information from a previous frame is buffered and provided to the current frame. A decision is made in the current frame whether pixel data from the previous frame may be reused. In one implementation if the speed of pixels in a tile is less than a quasi-static speed threshold a decision is made whether or not to reuse a fraction of pixels from the previous frame.Type: GrantFiled: June 18, 2015Date of Patent: November 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Abhinav Golas, Karthik Ramani, John W. Brothers
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Patent number: 9754344Abstract: A graphics processing operation may include a set of render target operations, in which render targets are read and one or more intermediate computations are performed before generating final render target output. A method of performing graphics processing includes determining a dependency between render targets and defining a scheduling of tiles to reduce or eliminate a need to write intermediate computations to external memory. An interleaved order may be determined to maintain intermediate computations of dependent render target operations in an on-chip cache hierarchy.Type: GrantFiled: March 11, 2015Date of Patent: September 5, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: John W. Brothers, Santosh Abraham
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Patent number: 9652817Abstract: In a pipelined application having different stages of processing, such as a graphics application or an image processing application, there may be a dependence of one compute kernel upon another. Data associated with individual kernels needs to be written and read. A technique to minimize a need to read and write kernel data to external memory utilize at least one of fusing kernels, resizing workgroups, and performing interleaving of kernels.Type: GrantFiled: March 12, 2015Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: John W. Brothers, Santosh Abraham, Joohoon Lee, Abhinav Golas, Seonggun Kim