Abstract: Signal processing may include determining a first component common to a first input signal and a second input signal and extracting the first component from at least one of the first input signal or the second input signal, a second component from the first input signal, and a second component from the second input signal. The second component of the first input signal may be different from the second component of the second input signal. An operation may be performed using the extracted, second components. The first component may be combined with a result of the operation.

Abstract: Methods and apparatus for facilitating motion estimation in video processing are provided. Preferably, coordinates of a search area within a video frame are determined for each of a plurality of macroblocks (MBs) of a reference frame based upon a predicted location derived from the coordinates of the MB within the reference frame and motion estimation information. The video frame can be segmented into tiles and associated overlapping tile defined for at least some tiles. Search data is defined for each tile as pel data for each pixel within that tile and any associated tile. Macroblock searches are preferably conducted on a tile assignment basis with tile search assignments distributed among a plurality of processing elements. Each processing element preferably has a local memory it uses for the search data when performing a tile search assignment.

Abstract: Provided is a method for improving performance of a processor. The method includes computing utilization values of components within the processor and determining a maximum utilization value based upon the computed utilization values. The method also includes comparing (i) the maximum utilization value with a first threshold and (ii) differences between the computed utilization values and a second threshold.

Abstract: Various methods, computer-readable mediums and apparatus are disclosed. In one aspect, a method of generating a graphical image on a display device is provided that includes splitting geometry level processing of the image between plural processors coupled to an interposer. Primitives are created using each of the plural processors. Any primitives not needed to render the image are discarded. The image is rasterized using each of the plural processors. A portion of the image is rendered using one of the plural processors and any remaining portion of the image using one or more of the other plural processors.

Abstract: A processing unit package includes a processing unit disposed on an interposer and a device protocol translator disposed on the interposer. Through-silicon vias (TSVs) may be used to provide connections from the device protocol translator through the interposer to an external device. The device protocol translator uses a controller to control a plurality of buffers that store information received from respective information buses coupled to the processing unit, such that the processing unit information is translated according to a protocol of the external device.

Abstract: Methods and apparatus for facilitating motion estimation in video processing are provided. Preferably, coordinates of a search area within a video frame are determined for each of a plurality of macroblocks (MBs) of a reference frame based upon a predicted location derived from the coordinates of the MB within the reference frame and motion estimation information. The video frame can be segmented into tiles and associated overlapping tile defined for at least some tiles. Search data is defined for each tile as pel data for each pixel within that tile and any associated tile. Macroblock searches are preferably conducted on a tile assignment basis with tile search assignments distributed among a plurality of processing elements. Each processing element preferably has a local memory it uses for the search data when performing a tile search assignment.

Abstract: A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed blocks and then performs on-the-fly decompression of the blocks. The decompressed blocks are then processed as usual by a texture consuming shader processor of the GPU.

Abstract: A device calculates a display color based on a true color, a fog color, and a distance z. The device uses two single-port memories, an arithmetic circuit, and a color blending circuit. Based on the distance z, two sampled values of a fog function are read from the single-port memories, one value from each memory. The arithmetic circuit calculates an approximate value of the fog function corresponding to the distance z based on the two sampled values of the fog function. The color blending circuit calculates the display color by blending the true color and the fog color according to the approximate value of the fog function.

Abstract: A method of providing specular highlights to 3D graphics using Phong illumination calculations spaces the pixels subject to the calculations apart in direct relationship to the number of lights contributing to the highlights. Linear, quadratic, or cubic attenuation is then applied to interpolate the values for the pixels not subject to the calculations.

Abstract: A write blocking accelerator provides maximum concurrency between a central processing unit (CPU) and the accelerator by allowing writes to the front buffer of a dual-buffered system. The CPU issues a series of drawing commands followed by a "page flip" command. When a command parser within the accelerator receives a page flip command, it notifies a screen refresh unit reading from the front buffer that the command was received. The screen refresh unit signals a memory interface unit (MIU) to enter a write blocking mode and provides the address of the current line in the front buffer from which the screen refresh unit is reading, and the address of the last line in the front buffer. The MIU blocks all writes from drawing engines that fall into the range defined between the two addresses. The screen refresh sends updated front buffer addresses to the MIU as display data is read out of the front buffer. Accordingly, the blocked address range constantly shrinks until all writes are allowed by the MIU.