Patents by Inventor John W. Fattaruso
John W. Fattaruso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7777531Abstract: A method and apparatus for providing a low power low voltage differential signaling driver are disclosed. In an example, a low voltage differential signaling driver circuit is described, comprising a first current source to provide current to a first differential pair of PNP transistors, a pair of transresistance amplifiers driven by a corresponding pair of transconductance stages, a second current source to provide current to a second differential pair of PNP transistors, and an output port having a common mode output voltage and a differential output voltage based on a state of the first differential pair of PNP transistors and the second differential pair of PNP transistors.Type: GrantFiled: April 18, 2008Date of Patent: August 17, 2010Assignee: Texas Instruments IncorporatedInventor: John W. Fattaruso
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Patent number: 7535280Abstract: An apparatus for shifting a received signal at a first reference level to an output signal at a second reference level; the received signal including information-indicating signal values; includes: (a) an input locus for receiving the received signal; (b) an output locus for presenting the output signal; (c) a first signal-handling circuit coupled with the input locus and with the output locus and setting the second reference level at the output locus; and (d) a second signal-handling circuit coupled with the input locus and with the first signal-handling circuit; the first signal-handling circuit and the second signal-handling circuit cooperating to convey the information-indicating signal values from the input locus to the output locus.Type: GrantFiled: April 30, 2004Date of Patent: May 19, 2009Assignee: Texas Instruments IncorporatedInventors: John W. Fattaruso, Benjamin J. Sheahan
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Patent number: 7116169Abstract: A driver apparatus comprising a signal switching circuit coupled for receiving an actuation signal and generating a first and a second control signal in response to the actuation signal; a first control circuit and a second control circuit coupled with the signal switching circuit; the first and second control circuits generating first and second drive control signals in response to the first and second control signals; first and second current generating circuits coupled with the first and second control circuits and coupled with a lower voltage rail; the first and second current generating circuits presenting first and second drive signals at first and second output loci in response to the first and second drive control signals.Type: GrantFiled: June 10, 2004Date of Patent: October 3, 2006Assignee: Texas Instruments IncorporatedInventor: John W. Fattaruso
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Patent number: 6927632Abstract: A low distortion compression amplifier comprising an amplifier circuit having an input and an output, wherein an input signal is received at the input and amplified in accordance with a gain to form an output signal at the output. The amplifier circuit further comprises a comparator circuit operable to receive the output signal and generate a first control signal in response thereto. A digital gain control circuit is coupled to the amplifier circuit, and is operable to generate a digital gain control signal based at least in part on the first control signal. The gain control signal is then employed to modulate the gain of the amplifier circuit in a digital fashion. The invention also comprises a method of digitally controlling a gain associated with an amplifier circuit. The method comprises comparing an output signal to a threshold and modulating the gain in a digital fashion, wherein the gain is modulated up in a plurality of rates or down in a plurality of rates in response to the comparison.Type: GrantFiled: June 20, 2002Date of Patent: August 9, 2005Assignee: Texas Instruments IncorporatedInventors: Walter Paul Sjursen, Daramana G. Gata, John W. Fattaruso
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Patent number: 6903615Abstract: A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60).Type: GrantFiled: September 23, 1999Date of Patent: June 7, 2005Assignee: Texas Instruments IncorporatedInventors: Paul E. Landman, Wai Lee, John W. Fattaruso, Michael de Wit
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Patent number: 6870389Abstract: A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair Q5 and Q6 having a tail current source I56; a first buffer Q3 providing a first input to the differential pair; a second buffer Q4 providing a second input to the differential pair; a first current absorbing device Q7 coupled to the tail current source I56 and having a control node SP capacitively coupled to the first buffer Q3; and a second current absorbing device Q8 coupled to the tail current source I56 and having a control node SM capacitively coupled to the second buffer Q4.Type: GrantFiled: June 6, 2003Date of Patent: March 22, 2005Assignee: Texas Instruments IncorporatedInventor: John W. Fattaruso
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Patent number: 6850104Abstract: A latch device is provided having a latch mode and a transparent mode. In the latch mode, the latch device synchronizes a data signal to a clock signal. In the transparent mode, the data signal drives the output without clock synchronization, such that the clock input signal is unused. The latch device can be employed in an optical driver for optical network laser diodes.Type: GrantFiled: March 10, 2003Date of Patent: February 1, 2005Assignee: Texas Instruments IncorporatedInventor: John W. Fattaruso
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Publication number: 20040246020Abstract: A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair Q5 and Q6 having a tail current source I56; a first buffer Q3 providing a first input to the differential pair; a second buffer Q4 providing a second input to the differential pair; a first current absorbing device Q7 coupled to the tail current source I56 and having a control node SP capacitively coupled to the first buffer Q3; and a second current absorbing device Q8 coupled to the tail current source I56 and having a control node SM capacitively coupled to the second buffer Q4.Type: ApplicationFiled: June 6, 2003Publication date: December 9, 2004Inventor: John W. Fattaruso
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Publication number: 20040179520Abstract: A latch device is provided having a latch mode and a transparent mode. In the latch mode, the latch device synchronizes a data signal to a clock signal. In the transparent mode, the data signal drives the output without clock synchronization, such that the clock input signal is unused. The latch device can be employed in an optical driver for optical network laser diodes.Type: ApplicationFiled: March 10, 2003Publication date: September 16, 2004Inventor: John W. Fattaruso
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Patent number: 6792019Abstract: The laser driver circuit includes an array of differential pairs 50 and 52. Each one of the differential pairs is coupled to a corresponding tail current source 67 and 69. The total modulation current for the laser driver circuit is developed as the sum of the output current from the array of differential pairs 50 and 52. Each of the tail current sources 67 and 69 generates a subrange of the total range of modulation current. The tail current in a given differential pair will then only vary over a small subrange of the total modulation current range, and the device size in each pair may be optimized to keep the emitter current density near the level that gives optimum bandwidth. This is equivalent to electrically increasing the emitter area of the composite differential pair as the total modulation current is increased, keeping current density approximately constant at its optimal level.Type: GrantFiled: January 21, 2003Date of Patent: September 14, 2004Assignee: Texas Instruments IncorporatedInventor: John W. Fattaruso
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Publication number: 20040000950Abstract: A low distortion compression amplifier comprising an amplifier circuit having an input and an output, wherein an input signal is received at the input and amplified in accordance with a gain to form an output signal at the output. The amplifier circuit further comprises a comparator circuit operable to receive the output signal and generate a first control signal in response thereto. A digital gain control circuit is coupled to the amplifier circuit, and is operable to generate a digital gain control signal based at least in part on the first control signal. The gain control signal is then employed to modulate the gain of the amplifier circuit in a digital fashion. The invention also comprises a method of digitally controlling a gain associated with an amplifier circuit. The method comprises comparing an output signal to a threshold and modulating the gain in a digital fashion, wherein the gain is modulated up in a plurality of rates or down in a plurality of rates in response to the comparison.Type: ApplicationFiled: June 20, 2002Publication date: January 1, 2004Inventors: Walter Paul Sjursen, Daramana G. Gata, John W. Fattaruso
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Publication number: 20030160636Abstract: The laser driver circuit includes an array of differential pairs 50 and 52. Each one of the differential pairs is coupled to a corresponding tail current source 67 and 69. The total modulation current for the laser driver circuit is developed as the sum of the output current from the array of differential pairs 50 and 52. Each of the tail current sources 67 and 69 generates a subrange of the total range of modulation current. The tail current in a given differential pair will then only vary over a small subrange of the total modulation current range, and the device size in each pair may be optimized to keep the emitter current density near the level that gives optimum bandwidth. This is equivalent to electrically increasing the emitter area of the composite differential pair as the total modulation current is increased, keeping current density approximately constant at its optimal level.Type: ApplicationFiled: January 21, 2003Publication date: August 28, 2003Inventor: John W. Fattaruso
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Patent number: 6388522Abstract: The opamp with common mode feedback bias includes: a first differential pair M1 and M2 having first and second inputs; active load devices M3 and M4 coupled to the first differential pair M1 and M2; a common mode feedback circuit 20 coupled to the active load devices M3 and M4 for controlling the active load devices M3 and M4; a second differential pair M18 and M19 having a first input coupled to the first input of the first differential pair M1 and M2 and a second input coupled to the second input of the first differential pair M1 and M2; and current drivers M22 and M23 having control nodes coupled to the second differential pair M18 and M19 and outputs coupled to the active load devices M3 and M4.Type: GrantFiled: August 17, 2001Date of Patent: May 14, 2002Assignee: Texas Instruments IncorporatedInventors: John W. Fattaruso, Daramana G. Gata
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Publication number: 20020024384Abstract: The opamp with common mode feedback bias includes: a first differential pair M1 and M2 having first and second inputs; active load devices M3 and M4 coupled to the first differential pair M1 and M2; a common mode feedback circuit 20 coupled to the active load devices M3 and M4 for controlling the active load devices M3 and M4; a second differential pair M18 and M19 having a first input coupled to the first input of the first differential pair M1 and M2 and a second input coupled to the second input of the first differential pair M1 and M2; and current drivers M22 and M23 having control nodes coupled to the second differential pair M18 and M19 and outputs coupled to the active load devices M3 and M4.Type: ApplicationFiled: August 17, 2001Publication date: February 28, 2002Inventors: John W. Fattaruso, Daramana G. Gata
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Patent number: 6348391Abstract: An integrated circuit and method of fabrication are disclosed for achieving electrical isolation between a spiral inductor and an underlying silicon substrate using standard semiconductor manufacturing process flow. A spiral conductor with square windings is formed in metal layer (20) patterned so that straight runs of successive turns (22, 23, 24) overlie corresponding runs of concentric square rings (16, 17, 18) formed in underlying metal layer (14). A unity gain voltage buffer (30) connects each ring (16, 17, 18) with a respective overlying turn (22, 23, 24).Type: GrantFiled: April 26, 2000Date of Patent: February 19, 2002Assignee: Texas Instruments IncorporatedInventor: John W. Fattaruso
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Publication number: 20020008589Abstract: A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60).Type: ApplicationFiled: September 23, 1999Publication date: January 24, 2002Inventors: PAUL E. LANOMAN, WAI LEE, JOHN W. FATTARUSO, MICHIEL DE WIT
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Patent number: 6307495Abstract: A conducting path with a path meander provides a precision voltage-dividing circuit. At each location wherein a voltage level is to be established, the conducting path has an expanded region called a junction region. The centers of all junction regions are equidistant from the centers of neighboring junction regions. Junction regions are positioned at predetermined intervals along the straight portions of the conducting path and at each corner of the path meander. Each junction region has a metal patch extending therefrom. The metal patches are coupled to conducting plugs that, in turn, can be coupled to switching elements of a digital-to-analog converter unit. The junction regions can be altered to increase the precision of the voltage-dividing circuit. Because the junction regions are equidistant from the neighboring junction regions, a cell that includes the switching elements can have a square geometry.Type: GrantFiled: April 14, 1999Date of Patent: October 23, 2001Assignee: Texas Instruments IncorporatedInventors: Shivaling S. Mahant-Shetti, John W. Fattaruso
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Patent number: 6268819Abstract: A data converter (20). The converter comprises an input (I0-I3) for receiving a digital word. The converter further comprises a string (22) of series connected resistive elements. The string comprises an integer number T of voltage taps (T0′-T8′). The converter further comprises an output (VOUT2) for providing an integer number P of different analog voltage levels in response to the digital word. The integer number P is greater than the integer number T.Type: GrantFiled: June 29, 1999Date of Patent: July 31, 2001Assignee: Texas Instruments CorporatedInventors: John W. Fattaruso, Shivaling S Mahant-Shetti
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Patent number: 6246352Abstract: An analog-to-digital converter (“ADC”, 40) comprising an input (VIN2) for receiving an input analog voltage. The ADC further comprises a digital-to-analog circuit, comprising a meandering string (12′) of series connected resistive elements (R0′-R14′) having a plurality of voltage taps (T0′-T15′), as well as a number of bit lines (BL0′-BL3′) and a number of word lines (WL0′-WL3′). For a given input analog voltage, the given input analog voltage is closest to a voltage at a selected one of the plurality of taps. In addition, the selected one of the plurality of taps is associated with one of the number of bit lines and one of the number of word lines. Additionally, the ADC further comprises a flash circuit (44, 46, 48, 50, 42, CAT0′-CAT3′) coupled to receive the input analog voltage from the input and in response to identify either the one of the number of bit lines or the one of the number of word lines.Type: GrantFiled: July 30, 1999Date of Patent: June 12, 2001Assignee: Texas Instruments IncorporatedInventors: John W. Fattaruso, Shivaling S Mahant-Shetti
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Patent number: 6239731Abstract: A data converter (20). The data converter comprises an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises at least one string (12′) of series connected resistive elements (R0′-R14′). The at least one string comprises a plurality of voltage taps (T0′-T14′)and is operable to receive a string bias of X volts (VREF2). Lastly, the data converter comprises a plurality of switching transistors (ST0n-ST15n; ST0p-ST15p) coupled between the plurality of voltage taps and the output. Specifically, responsive to at least a portion of the digital word, selected ones of the switching transistors are operable to receive a gate bias to enable the corresponding switching transistor to provide a conductive path from a corresponding one of the voltage taps toward the output. In addition, the difference between X volts and the gate bias is less than approximately 2.Type: GrantFiled: May 11, 1999Date of Patent: May 29, 2001Assignee: Texas Instruments IncorporatedInventors: John W. Fattaruso, Shivaling S Mahant-Shetti