Patents by Inventor John W. Osenbach

John W. Osenbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080116567
    Abstract: An assembly comprises a stiffener, a circuit substrate and an IC chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers at least a portion of the first region of the stiffener, while the IC chip overlies at least a portion of each of the first and second regions of the stiffener. The assembly further comprises a signal solder bump and a thermally conductive feature. The signal solder bump contacts the IC chip and the circuit substrate. The thermally conductive feature is disposed between, and is metallurgically bonded to, the integrated circuit chip and the second region of the stiffener. The thermally conductive feature provides an efficient thermal conductivity pathway between the IC chip and the stiffener.
    Type: Application
    Filed: November 22, 2006
    Publication date: May 22, 2008
    Inventors: Ahmed Amin, David L. Crouthamel, John W. Osenbach, Thomas H. Shilling, Brian T. Vaccaro
  • Publication number: 20080042302
    Abstract: The specification describes lidded IC plastic overmolded packages with chimney-type heat sinks. The packages have mechanical hold-down structures in the package lids that, when overmold is applied, form complementary hold-down structures in the overmold.
    Type: Application
    Filed: August 16, 2006
    Publication date: February 21, 2008
    Inventors: Robert B. Crispell, Robert Scott Kistler, John W. Osenbach
  • Publication number: 20080042262
    Abstract: The specification describes a lidded MCM IC plastic overmolded package with chimney-type heat sink. The lid is mechanically decoupled from the chimneys by a compliant conductive polymer plug.
    Type: Application
    Filed: August 16, 2006
    Publication date: February 21, 2008
    Inventors: Robert B. Crispell, Robert Scott Kistler, John W. Osenbach
  • Patent number: 6894400
    Abstract: Packages for electronic devices are formed from a die such as a silicon die in electrical communication with a substrate through a mating array, e.g. ball array, on the substrate. An underfill material is present between the die and substrate in the region of the array. For large dies (a dimension of 15 mm or greater) failure of the connection between the die and substrate is avoided by employing a particle filled underfill material with specifically chosen Young moduli both below and above the glass transition temperature of the underfill material.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: May 17, 2005
    Assignee: Agere Systems Inc.
    Inventors: Jason P. Goodelle, John W. Osenbach
  • Patent number: 6623176
    Abstract: An optical fiber assembly including a ferrule which increases the glass transition temperature of an entire epoxy system resident within the ferrule and a method for suppressing optical instabilities of an optoelectronic package are described. One or more openings are made in a ferrule body to allow reaction gases from the epoxy caused during curing to escape, allowing a greater portion of the epoxy to fully cure, thereby raising the glass transition temperature of the epoxy system.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: September 23, 2003
    Assignee: Triquint Technology Holding Co.
    Inventors: Curtis A. Jack, John W. Osenbach
  • Publication number: 20030100195
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device includes a semiconductor substrate and an indium doped dielectric layer located over the semiconductor substrate.
    Type: Application
    Filed: November 28, 2001
    Publication date: May 29, 2003
    Applicant: Agere Systems Inc.
    Inventors: Julia C. Duncan, William J. Minford, John W. Osenbach
  • Publication number: 20030068138
    Abstract: An optical fiber assembly including a ferrule which increases the glass transition temperature of an entire epoxy system resident within the ferrule and a method for suppressing optical instabilities of an optoelectronic package are described. One or more openings are made in a ferrule body to allow reaction gases from the epoxy caused during curing to escape, allowing a greater portion of the epoxy to fully cure, thereby raising the glass transition temperature of the epoxy system.
    Type: Application
    Filed: August 13, 2001
    Publication date: April 10, 2003
    Inventors: Curtis A. Jack, John W. Osenbach
  • Patent number: 6265757
    Abstract: A method for creating attached features while controlling the depth profile between the features is presented. First the features are formed with a separating barrier between the features. The separating barrier is then etched in a second step with an orientation dependent etchant to attach the two feature. This method can be used to create attached features of relative similar sizes or attached features of disparate sizes.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: July 24, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Michael F. Brady, Casimir R. Nijander, John W. Osenbach, Michael G. Palin, Aleksandra Yudina
  • Patent number: 6265240
    Abstract: A method and apparatus for passively aligning an optical element on an optical die wherein multiple potential mounting pads are supplied for potential mounting of the optical component. Appropriate tables are generated for 1) the response of the optical detecting component for a given light power level as a function of the mounting position of the optical detecting component, and 2) the asymmetry of the light generating component. Given the two tables an algorithm is prepared for automatically determining the appropriate mounting position to provide desired detection device response characteristics for any given light generating component to be mounted on the die.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: July 24, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: Mindaugas F. Dautartas, James F. Dormer, John W. Osenbach, Edward A. Pitman
  • Patent number: 5989354
    Abstract: The invention is a method for removing organic and other contaminants, such as photo-resist, from semi-conductor dies and micro-lenses by placing the dies in a solution of two parts ethylene, diamine tetra-acetic-acid (EDTA) to one part peroxide at a temperature of between 30.degree. and 55.degree. C., and preferably between 40.degree. and 44.degree. C., for a period of 1-30 minutes, and preferably between 2 and 10 minutes.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: November 23, 1999
    Assignee: Lucent Technologies, Inc.
    Inventors: James F. Dormer, John W. Osenbach
  • Patent number: 5583078
    Abstract: Re-entrant angles in doped dielectrics produced from the decomposition of organo-silicon compounds are reduced or eliminated by the addition of a polar molecule to the dielectric deposition process.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 10, 1996
    Assignee: Lucent Technologies Inc.
    Inventor: John W. Osenbach
  • Patent number: 5440575
    Abstract: Disclosed are high reliability semiconductor lasers that need not be maintained inside a hermetic enclosure. Such lasers can advantageously be used in a variety of applications, e.g., in optical fiber telecommunications, and in compact disc players. Such "non-hermetic" lasers comprise facet coatings that comprise a dielectric layer that has very low water saturation value. In preferred embodiments this dielectric layer is SiO.sub.x (1.ltoreq.x<2), deposited by a molecular beam method. Deposition conditions are selected to result in a dense material that is largely free of particulates and blisters, and is substantially impermeable to moisture. Among the deposition conditions is substantially normal beam incidence, and a relatively low deposition rate. Deposition is advantageously carried out under relatively high vacuum conditions. A quantitative method of determining the water level in a SiO.sub.x film is disclosed.
    Type: Grant
    Filed: April 6, 1994
    Date of Patent: August 8, 1995
    Assignee: AT&T Corp.
    Inventors: Naresh Chand, Robert B. Comizzoli, John W. Osenbach, Charles B. Roxlo, Won-Tien Tsang
  • Patent number: 5418190
    Abstract: A method of fabricating a semiconductor electro-optical device in which a cleaving apparatus is used to separate the wafer into bars of semiconductor material by striking the wafer from the epitaxial side, directly beneath the substrate side scribe mark. A series of angularly shaped trenches are etched across the epitaxial side of the semiconductor bars to permit bar separation into individual devices that allows a plurality of bars to be processed simultaneously.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: May 23, 1995
    Assignee: AT&T Corp.
    Inventors: Mark B. Cholewa, John W. Osenbach, Bryan P. Segner
  • Patent number: 5273621
    Abstract: A process for growing selective epitaxial layers on a silicon substrate. In a epitaxial growth reactor, hydrogen and the reactive gasses, the silicon source gas and hydrochloric acid, are introduced. The amount of silicon to free hydrochloric acid is controlled to be about 1:6 during the growth process and then turned off, the hydrogen remaining on. The resulting epitaxial layer may be grown over one micron in thickness with less than 0.1 micron of faceting. Further, a etchant of H.sub.2 O and HF diluted in NHO.sub.3 is first used to remove surface damage on the silicon substrate prior to epitaxial layer growth.
    Type: Grant
    Filed: August 26, 1992
    Date of Patent: December 28, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Anatoly Feygenson, John W. Osenbach, Donald G. Schimmel
  • Patent number: 5244821
    Abstract: A method for forming a bipolar transistor is disclosed. An optional thin screen oxide (.apprxeq.150 .ANG.) may be formed upon a substrate over an already-defined collector region. A BF.sub.2 or other implantation is performed through the screen oxide to create the base. The screen oxide is removed and replaced with a patterned high pressure oxide so that the emitter may be defined. The resulting device has a more controllable Gummel number and breakdown voltage.
    Type: Grant
    Filed: June 7, 1991
    Date of Patent: September 14, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Thomas E. Ham, John W. Osenbach, Morgan J. Thoma, Susan C. Vitkavage
  • Patent number: 5168089
    Abstract: A process for growing selective epitaxial layers on a silicon substrate. In a epitaxial growth reactor, hydrogen and the reactive gasses, the silicon source gas and hydrochloric acid, are introduced. The amount of silicon to free hydrochloric acid is controlled to be about 1:6 during the growth process and then turned off, the hydrogen remaining on. The resulting epitaxial layer may be grown over one micron in thickness with less than 0.1 micron of faceting. Further, a etchant of H.sub.2 O and HF diluted in NHO.sub.3 is first used to remove surface damage on the silicon substrate prior to epitaxial layer growth.
    Type: Grant
    Filed: May 13, 1991
    Date of Patent: December 1, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Anatoly Feyenson, John W. Osenbach, Donald G. Schimmel
  • Patent number: 5107323
    Abstract: A semi-insulating layer is formed over a high voltage device in order to protect the device substrate from charge buildup. A layer comprising silicon oxynitride is deposited over the semi-insulating layer in order to prevent arcing between device electrodes and provide corrosion resistance.
    Type: Grant
    Filed: May 16, 1991
    Date of Patent: April 21, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: William R. Knolle, John W. Osenbach
  • Patent number: H665
    Abstract: A high voltage silicon device with a resistive field shield comprising semi-insulating silicon nitride (sin-SiN). The N/Si ratio is controlled to provide the resistive field shield with the desired conductivity. This resistive field shield material may also serve as an outer protection layer for the device.
    Type: Grant
    Filed: October 19, 1987
    Date of Patent: August 1, 1989
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: William R. Knolle, John W. Osenbach