Abstract: A mechanism that includes an apparatus and method for ensuring that all transactions within any flow control class completes is herein provided. The mechanism includes a plunge transaction that is inserted in each pending transaction queue and which is transmitted to a particular destination device. All prior transactions in a flow control class are deemed to be complete when the destination device receives the plunge transactions in the flow control class.

Abstract: An apparatus and method using a valid bit in a cache entry address first-in-first-out (FIFO) to indicate when a cache entry can be flushed in a coherent memory domain. One embodiment of the invention involves a method for tracking a cache entry in a cache serving data transfers between a coherent memory domain and a non-coherent memory domain in a data processing system, including steps of storing an address corresponding to a cache entry in a FIFO register, using at least one register cell as a valid flag to indicate when the cache entry is still in the cache, and changing the valid flag based on one or more signals transmitted from the non-coherent memory domain.

Abstract: A method and apparatus determines completion of all of one or more operations for a particular input/output device initiated prior to an inquiry start time. The method provides one or more in-progress bits and an equal number of snapshot bits. Each in-progress bit corresponds to a respective associated operation for the input/output device. An in-progress bit is set when the associated operation is initiated. The in-progress bit is cleared when the associated operation is completed. The method copies, at the inquiry start time, all of the in-progress bits to the corresponding snapshot bits and clears a snapshot bit when the associated operations is completed. Finally, the method determines whether every one of said one or more snapshot bits is cleared. The apparatus comprises an input/output operator, one or more operation requesters, one or more in-progress bits and an equal number of snapshot bits. Preferably, the in-progress bits are grouped in a register, as are the snapshot bits.

Abstract: A cache status data structure in a cache memory system provides a large amount of status data, which various requesters, e.g., processors and I/O devices, may read, modify and/or write to, in order to allows flexibility in the manner in which the various requesters access the cache memory. The cache status data structure is implemented as a cache structure block having a plurality of cache status bits for each cache line of the cache memory. The cache status block comprises one or more read port and one or more write port, from which, upon presenting the line entry number of the cache line of interest, a requester may read and/or write back modified status bits. The cache status bits in the cache data structure includes include a significant amount of information, including, e.g.

Abstract: A cache memory replacement algorithm replaces cache lines based on the likelihood that cache lines will not be needed soon. A cache memory in accordance with the present invention includes a plurality of cache lines that are accessed associatively, with a count entry associated with each cache line storing a count value that defines a replacement class. The count entry is typically loaded with a count value when the cache line is accessed, with the count value indicating the likelihood that the contents of cache lines will be needed soon. In other words, data which is likely to be needed soon is assigned a higher replacement class, while data that is more speculative and less likely to be needed soon is assigned a lower replacement class. When the cache memory becomes full, the replacement algorithm selects for replacement those cache lines having the lowest replacement class.

Abstract: A method and apparatus forces synchronous operation in a system that determines a phase-based relationship between two clocks by providing selectable delays of clock and data signals. A sending IC transmits data to the receiving IC over a data bus, and provides a strobe (clock) signal to validate data at the receiving IC. The phase relationship between the strobe signal and the internal clock of receiving IC is initially unknown. Within the receiving IC, the strobe signal is used to form four clock signals that clock data into four flip flops using a round robin scheme. Each of the round robin flip flops has a valid read window, and pair of multiplexors route the outputs of the round robin flip flops to a pair of flip flops that are clocked using internal clocks of the receiving IC. A select signal in the clock domain of the receiving IC is provided to the pair of multiplexors. The select signal can have one of two possible orientations. A phase detection circuit selects the proper orientation.

Abstract: A cache memory replacement algorithm replaces cache lines based on the likelihood that cache lines will not be needed soon. A cache memory in accordance with the present invention includes a plurality of cache lines that are accessed associatively, with a count entry associated with each cache line storing a count value that defines a replacement class. The count entry is typically loaded with a count value when the cache line is accessed, with the count value indicating the likelihood that the contents of cache lines will be needed soon. In other words, data which is likely to be needed soon is assigned a higher replacement class, while data that is more speculative and less likely to be needed soon is assigned a lower replacement class. When the cache memory becomes full, the replacement algorithm selects for replacement those cache lines having the lowest replacement class.

Abstract: A method and apparatus in accordance with the present invention uses the unused bits of a data packet to transmit additional information by piggy-backing "secondary" code words into a data packet containing a "primary" code word. A secondary code word may be piggy-backed into a data packet containing a primary code word when the primary code word and any secondary code words already stored in the data packet leave sufficient unused space in the data packet to store an additional secondary code word, and the route traveled by the data packet as the packet is routed to the network node addressed by the primary code passes through (or ends at) the network node addressed by the secondary code word, or passes through (or ends at) a network node that can relay the secondary code word to the network node addressed by the secondary code word. In a first embodiment, an ECC is generated for the primary code word using a predefined bit pattern (such as all 0's) for any unused bit positions in the data packet.

Abstract: A control system providing a control of position, velocity, and direction of movement of a member in an axis of freedom which employs a scale having scale divisions thereon and bands or zones defining limits of constant velocity control, acceleration and deceleration zone limits, and a rest or parking position. The scale spans and parallels the axis of freedom. A single channel transducer or encoder mounted on and moving with the member produces time varying output signals in response to the sensing of scale divisions along the scale and signals of different characteristic in response to encoder sensing of the limit bands. The time varying output signals are employed as scale division count signals for position determination and as scale division count signals per unit of time, for velocity feedback.