Patents by Inventor John Zolnowsky
John Zolnowsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5991790Abstract: A system for properly delivering an signals in a computer system. A first module is called which waits for a signal to be generated. Upon a signal being generated, the first module is notified of the signal's generation. The first module then directs the signal to a second module, and causes the signal to be delivered to the second module.Type: GrantFiled: July 1, 1996Date of Patent: November 23, 1999Assignee: Sun Microsystems, Inc.Inventors: Devang K. Shah, John Zolnowsky
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Patent number: 5021991Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 18, 1987Date of Patent: June 4, 1991Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, John Zolnowsky, David Mothersole
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Patent number: 4994961Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 18, 1987Date of Patent: February 19, 1991Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, John Zolnowsky, David Mothersole
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Patent number: 4914578Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: January 31, 1986Date of Patent: April 3, 1990Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, David Mothersole, John Zolnowsky
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Patent number: 4890223Abstract: A paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU assembling each of the logical addresses and the corresponding physical address into a respective translator.Type: GrantFiled: July 21, 1988Date of Patent: December 26, 1989Assignee: Motorola, Inc.Inventors: Michael W. Cruess, William C. Moyer, John Zolnowsky
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Patent number: 4821231Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word, Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives whcih define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: December 21, 1987Date of Patent: April 11, 1989Assignee: Motorola, Inc.Inventors: Michael Cruess, David Mothersole, John Zolnowsky, Douglas B. MacGregor
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Patent number: 4811274Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 14, 1987Date of Patent: March 7, 1989Assignee: Motorola, Inc.Inventors: Michael Cruess, David Mothersole, John Zolnowsky, Douglas B. MacGregor
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Patent number: 4800489Abstract: A paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining a first portion of the logical address and a first table pointer to access a first one of the pointer tables to obtain therefrom a page table pointer to a selected one of the page tables and then combining a second portion of the logical address and the page table pointer to access the selected page table to obtain therefrom the physical address. If desired, an address space selector may be considered as an extension of the logical address.Type: GrantFiled: May 19, 1988Date of Patent: January 24, 1989Assignee: Motorola, Inc.Inventors: William C. Moyer, Michael W. Cruess, William M. Keshlear, John Zolnowsky
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Patent number: 4766537Abstract: A paged memory management unit (PMMU) adapted to prevent unauthorized access by a calling module executing in a data processor to a called module having a higher access level. A Stack Change Control Register in the PMMU has a bit corresponding to each valid access level. If the PMMU determines that any bit in the Stack Change Control Register corresponding to an access level between the access level of the calling module and the called module, including the access level of the called module, is set, a Change Stack bit in a Status Register is set to indicate that the processor should allocate a new stack for the called module. Both the Stack Change Control Register and the Status Register are accessible to the processor.Type: GrantFiled: January 2, 1986Date of Patent: August 23, 1988Assignee: Motorola, Inc.Inventor: John Zolnowsky
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Patent number: 4763244Abstract: A paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining a first portion of the logical address and a first table pointer to access a first one of the pointer tables to obtain therefrom a page table pointer to a selected one of the page tables and then combining a second portion of the logical address and the page table pointer to access the selected page table to obtain therefrom the physical address. If desired, an address space selector may be considered as an extension of the logical address.Type: GrantFiled: January 15, 1986Date of Patent: August 9, 1988Assignee: Motorola, Inc.Inventors: William C. Moyer, Michael W. Cruess, William M. Keshlear, John Zolnowsky
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Patent number: 4763250Abstract: In a paged memory management unit (PMMU), a translation control (TC) register contains a set of table indexes which define the number of bits of the logical address to be used to access the translation table at the respective levels. The TC register also contains an initial shift field which defines the number of high order bits of the logical address to be discarded before an address translation, and a page size field which defines the number of low order bits of the logical address comprising the page address. Each descriptor in each translation table contains a descriptor type field which defines whether that particular descriptor is a translation descriptor or a pointer descriptor. If a pointer descriptor is encountered at a table level other than the lowest level, the translation table walk is terminated early and the translation performed using that pointer descriptor. In general, a table may occupy either the lower or upper portions of the page in which such table is stored.Type: GrantFiled: April 1, 1985Date of Patent: August 9, 1988Assignee: Motorola, Inc.Inventors: William M. Keshlear, William C. Moyer, John Zolnowsky
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Patent number: 4758978Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 18, 1986Date of Patent: July 19, 1988Assignee: Motorola, Inc.Inventors: Michael Cruess, David Mothersole, John Zolnowsky, Douglas B. MacGregor
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Patent number: 4757445Abstract: A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.Type: GrantFiled: July 29, 1987Date of Patent: July 12, 1988Assignee: Motorola, Inc.Inventors: John Zolnowsky, Lester M. Crudele, Michael E. Spak
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Patent number: 4750110Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: April 18, 1983Date of Patent: June 7, 1988Assignee: Motorola, Inc.Inventors: David Mothersole, John Zolnowsky, Douglas B. MacGregor
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Patent number: 4740889Abstract: A data processor is adapted for operation with a memory containing a plurality of items of operating information for the data processor. In addition a cache stores a selected number of all of the items of the operating information. When the cache provides an item of operating information, the memory is not requested to provide the item so that a user of the data processor cannot detect the request for the item. A disable circuit is provided to prevent the cache from providing the item when a signal external to the data processor is provided. Consequently, a user, with the external signal, can cause the data processor to make all of its requests for items of operating information to the memory where these requests can be detected.Type: GrantFiled: July 14, 1986Date of Patent: April 26, 1988Assignee: Motorola, Inc.Inventors: David S. Motersole, Jay A. Hartvigsen, John Zolnowsky
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Patent number: 4731736Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 18, 1986Date of Patent: March 15, 1988Assignee: Motorola, Inc.Inventors: David Mothersole, Douglas B. MacGregor, John Zolnowsky
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Patent number: 4729094Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: March 24, 1987Date of Patent: March 1, 1988Assignee: Motorola, Inc.Inventors: John Zolnowsky, David S. Mothersole, Douglas B. MacGregor, William C. Moyer
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Patent number: 4719567Abstract: A bus master is prevented from utilizing a communication bus during a current sample interval if the utilization rate of the communication bus during the immediately preceeding sample interval exceeded a selected limit.Type: GrantFiled: April 29, 1982Date of Patent: January 12, 1988Assignee: Motorola, Inc.Inventors: Charles L. Whittington, John Zolnowsky
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Patent number: 4715013Abstract: A system for interfacing a processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: July 25, 1986Date of Patent: December 22, 1987Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, John Zolnowsky, David Mothersole
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Patent number: 4710866Abstract: A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.Type: GrantFiled: October 7, 1986Date of Patent: December 1, 1987Assignee: Motorola, Inc.Inventors: John Zolnowsky, Lester M. Crudele, Michael E. Spak