Abstract: A bus master is provided with the capability to accept a data transfer task from a CPU, which includes the performance of a predetermined sequence of data transfer operations between memory and a selected peripheral controlled by a respective controller. During any one of the operations, the bus master may be requested to relinquish the bus so that a higher priority transfer may occur or a deadlock condition resolved. In response to such request, the bus master immediately terminates the current bus cycle, but remembers the state thereof at the time of relinquishment. After the high priority transfer is completed, the bus master may be allowed to rearbitrate for use of the bus. Upon again obtaining control of the bus, the bus master restarts the bus cycle which was prematurely terminated and continues the sequence of operations as if no relinquishment had occurred.

Abstract: In a data processing system having linked lists it is useful to be able to add and delete items from such lists while maintaining the integrity of the linked nature of such lists. A new compare and swap instruction provides for effectively simultaneously swapping 2 values which is useful for safely adding and deleting items from linked lists. Prior to the instruction the status of the two value are read at the locations to be swapped. During the instruction these locations are checked again to ensure that no change has occurred at these locations before the instruction performs the swap of the two new values. The instruction then performs the proposed 2 value swap but only if no change has occurred at these two locations where the swap is to be performed.

Abstract: A typical feature of a data processor is a bounds check. A bounds check is achieved when a determination is made as to whether a check value, typically an address or datum, is within predetermined bounds. Such check values may be signed or unsigned. By requiring that the upper bound be numerically larger than the lower bound for doing a signed check, and requiring that the upper bound be logically larger than the lower bound for doing an unsigned check, the bounds check is performed by the data processor without the need of receiving a signal which informs the data processor in advance as to whether the check is to be signed or unsigned.

Abstract: A pipelined data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. In response to detecting a particular sequence of a loopable instruction followed by a conditional branch instruction which selectively branches back to the loopable instruction, the data processor enters a loop mode wherein the loopable instruction and the branch instruction are internally recirculated around the pipeline to save instruction fetch cycles.