Patents by Inventor Johnny Chan
Johnny Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230289143Abstract: A memory device and a computing method are provided. The memory device includes a memory array, comprising a first and second memory blocks, and a comparator. The first memory block performs a multiplication and accumulation (MAC) operation according to a first weight matrix and a first input matrix to generate a first sum. The second memory block performs the MAC operation according to a second weight matrix and a second input matrix to generate a second sum. The comparator compares the first and second sums. In a first configuration, each value of the input and second input matrixes are the same and each value of the first and second weight matrixes are complements. In a second configuration, each value of the first and second input matrixes are complements and each value of the first and second weight matrixes are the same.Type: ApplicationFiled: March 13, 2022Publication date: September 14, 2023Applicant: Winbond Electronics Corp.Inventors: Johnny Chan, Chi-Shun Lin
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Patent number: 11600346Abstract: A write cycle recording device includes a storage device and a controller. The storage device is corresponding to a memory block of a non-volatile memory. The storage device has a plurality of bits for recording a plurality of recorded writing loop counts corresponding to a plurality of writing operations of the memory block. The controller is configured to: perform a writing operation on the memory block; record a performed writing loop count of the writing operation; and, update a recorded writing loop count corresponding to the writing operation in the storage device according to the performed writing loop count.Type: GrantFiled: June 3, 2021Date of Patent: March 7, 2023Assignee: Winbond Electronics Corp.Inventors: Johnny Chan, Chi-Shun Lin
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Publication number: 20220392557Abstract: A write cycle recording device includes a storage device and a controller. The storage device is corresponding to a memory block of a non-volatile memory. The storage device has a plurality of bits for recording a plurality of recorded writing loop counts corresponding to a plurality of writing operations of the memory block. The controller is configured to: perform a writing operation on the memory block; record a performed writing loop count of the writing operation; and, update a recorded writing loop count corresponding to the writing operation in the storage device according to the performed writing loop count.Type: ApplicationFiled: June 3, 2021Publication date: December 8, 2022Applicant: Winbond Electronics Corp.Inventors: Johnny Chan, Chi-Shun Lin
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Patent number: 10579290Abstract: An option code providing circuit includes a plurality of resistive random access memory cells and a controller. The controller determines whether to provide a control signal to operate a heavy forming operation on the resistive random access memory cells or not. Wherein, the controller performs a read operation on the resistive random access memory cells to determine a bit number of the resistive random memory cell which is heavy formed, and the option code is determined by the bit number of resistive random access memory cell which is heavy formed or a bit number of the resistive random access memory cell which is not heavy formed.Type: GrantFiled: March 23, 2016Date of Patent: March 3, 2020Assignee: Winbond Electronics Corp.Inventors: Johnny Chan, Chi-Shun Lin
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Patent number: 10276259Abstract: A memory testing method for testing a memory apparatus configured with an auxiliary testing circuit is provided. The memory testing method includes: reading a test data from a memory array of the memory; and encoding the test data into an encoded data by the auxiliary testing circuit, wherein the encoded data comprises a first piece data and a second piece data. The encoded data is encoded to include a first piece data and a second piece data, where the first piece data indicates a number of a binary state in the read test data, and the second piece data indicates an error bit in the read test data. In addition, a memory apparatus for the memory testing method is also provided.Type: GrantFiled: July 5, 2017Date of Patent: April 30, 2019Assignee: Winbond Electronics Corp.Inventor: Johnny Chan
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Publication number: 20190013084Abstract: A memory testing method for testing a memory apparatus configured with an auxiliary testing circuit is provided. The memory testing method includes: reading a test data from a memory array of the memory; and encoding the test data into an encoded data by the auxiliary testing circuit, wherein the encoded data comprises a first piece data and a second piece data. The encoded data is encoded to include a first piece data and a second piece data, where the first piece data indicates a number of a binary state in the read test data, and the second piece data indicates an error bit in the read test data. In addition, a memory apparatus for the memory testing method is also provided.Type: ApplicationFiled: July 5, 2017Publication date: January 10, 2019Applicant: Winbond Electronics Corp.Inventor: Johnny Chan
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Patent number: 10152276Abstract: A memory device includes a memory array including a plurality of memory cells that store data, a sense circuit coupled to the memory array for reading data stored in the memory array, a data register for storing data to be written into the memory array, a data processor, and a control unit. The data processor is configured to receive input data units to be written into the memory array, and process the input data units based on array data units stored in the memory array to generate processed data units. The control unit is configured to write the processed data units into the memory array.Type: GrantFiled: July 18, 2016Date of Patent: December 11, 2018Assignee: Winbond Electronics CorporationInventor: Johnny Chan
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Publication number: 20180025757Abstract: A memory device includes a memory array storing data, a sense amplifier configured to read a plurality of data bits from the memory array and output a sense data signal including the data bits read from the memory array, a data multiplexer configured to receive the sense data signal and generate a plurality of group signals, a plurality of local data registers coupled to the data multiplexer, at least one of the local data registers being configured to generate a serial data output signal according to an output mode, and a plurality of output circuits coupled to respective ones of the plurality of local data registers, at least one of the output circuits being configured to receive the serial data output signal output from the at least one of the local data registers and sequentially output the data bits included in the serial data output signal.Type: ApplicationFiled: July 19, 2016Publication date: January 25, 2018Inventors: Johnny CHAN, Tinwai WONG
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Publication number: 20180018132Abstract: A memory device includes a memory array including a plurality of memory cells that store data, a sense circuit coupled to the memory array for reading data stored in the memory array, a data register for storing data to be written into the memory array, a data processor, and a control unit. The data processor is configured to receive input data units to be written into the memory array, and process the input data units based on array data units stored in the memory array to generate processed data units. The control unit is configured to write the processed data units into the memory array.Type: ApplicationFiled: July 18, 2016Publication date: January 18, 2018Inventor: Johnny CHAN
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Publication number: 20170277465Abstract: An option code providing circuit includes a plurality of resistive random access memory cells and a controller. The controller determines whether to provide a control signal to operate a heavy forming operation on the resistive random access memory cells or not. Wherein, the controller performs a read operation on the resistive random access memory cells to determine a bit number of the resistive random memory cell which is heavy formed, and the option code is determined by the bit number of resistive random access memory cell which is heavy formed or a bit number of the resistive random access memory cell which is not heavy formed.Type: ApplicationFiled: March 23, 2016Publication date: September 28, 2017Inventors: Johnny Chan, Chi-Shun Lin
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Patent number: 9627091Abstract: A memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in rows and columns, a plurality of word lines extending in a row direction and coupled to respective rows of the memory cells, and a plurality of local bit lines extending in a column direction and coupled to respective columns of the memory cells. The control unit is configured to program a selected one of the rows of memory cells to have a predetermined pattern of digital states, couple selected ones of the local bit lines to a global bit line and couple unselected ones of the local bit lines to ground based on the predetermined pattern, apply a stress voltage to the global bit line, and after a predetermined period of time, sense the digital states of the selected row of memory cells.Type: GrantFiled: July 18, 2016Date of Patent: April 18, 2017Assignee: Winbond Electronics CorporationInventors: Johnny Chan, Hsi-Hsien Hung
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Patent number: 9576652Abstract: The invention provides a resistive memory apparatus including at least one first resistive memory cell, a first bit line selecting switch, a first source line selecting switch, a first pull down switch and a second pull down switch. The first bit line selecting switch is coupled between a first bit line and a sense amplifier. The first source line selecting switch is coupled between a source line and the sense amplifier. The first and second pull down switches are respectively coupled to the bit line and source line. When a reading operation is operated, on or off statuses of the first bit line selecting switch and the second pull down switch are the same, on or off statuses of the first source line selecting switch and the first pull down switch are the same, and on or off statuses of the first and second pull down switches are complementary.Type: GrantFiled: January 11, 2016Date of Patent: February 21, 2017Assignee: Winbond Electronics Corp.Inventors: Seow-Fong Lim, Johnny Chan, Douk-Hyoun Ryu, Chi-Shun Lin
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Patent number: 9377501Abstract: The invention provides a semiconductor wafer with a die area and a scribe area, and the semiconductor wafer includes a die and a testing circuit. The die is formed on the die region of the semiconductor wafer, and the die includes a main circuit. The testing circuit is disposed on the scribe area of the semiconductor wafer, and is electrically connected to the die for testing the main circuit.Type: GrantFiled: February 12, 2014Date of Patent: June 28, 2016Assignee: WINBOND ELECTRONICS CORP.Inventors: Hsi-Hsien Hung, Johnny Chan, Dennis Cheng
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Patent number: 9348572Abstract: In an embodiment, a method comprises transmitting, from a mobile computing device to a server computer, first data identifying a selection at the mobile computing device of an app that is not associated with an identification module associated with the server computer that would allow the server computer to identify the device; receiving, at the mobile computing device from the server computer, second data identifying zero or more apps lacking the identification module that have been selected previously using the mobile computing device; determining whether a protocol handler for each of the zero or more apps lacking the identification module is in the mobile computing device; in response to determining that a particular protocol handler for one of the apps is in the mobile computing device, transmitting to the server computer a message specifying that the particular protocol handler is in the mobile computing device; communicating a reward to any of: a particular one of the apps that is associated with the pType: GrantFiled: March 12, 2014Date of Patent: May 24, 2016Assignee: Tapjoy, Inc.Inventors: Christopher Paul Farm, Brian Stebar, Johnny Chan, Steve Tan
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Patent number: 9214211Abstract: Respective die IDs are determined for a plurality of memory die commonly packaged as a memory device based on their respective Unique Identifiers (“UIDs”). An external controller initiates an internal Die ID (“DID”) determination process in which each die eventually asserts a signal on its inter-die signaling pin after a number of clocks as determined by its UID, and assigns itself a Die ID based on the number of signals asserted by other die prior to its own signaling response. Each die keeps track of the number of signals asserted by the other die prior to its own signaling response, as well as, optionally, the total number of signals on the signaling pin to determine the package die count for the device.Type: GrantFiled: May 15, 2014Date of Patent: December 15, 2015Assignee: WINBOND ELECTRONICS CORPORATIONInventor: Johnny Chan
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Publication number: 20150332747Abstract: Respective die IDs are determined for a plurality of memory die commonly packaged as a memory device based on their respective Unique Identifiers (“UIDs”). An external controller initiates an internal Die ID (“DID”) determination process in which each die eventually asserts a signal on its inter-die signaling pin after a number of clocks as determined by its UID, and assigns itself a Die ID based on the number of signals asserted by other die prior to its own signaling response. Each die keeps track of the number of signals asserted by the other die prior to its own signaling response, as well as, optionally, the total number of signals on the signaling pin to determine the package die count for the device.Type: ApplicationFiled: May 15, 2014Publication date: November 19, 2015Applicant: WINBOND ELECTRONICS CORPORATIONInventor: Johnny Chan
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Publication number: 20150226785Abstract: The invention provides a semiconductor wafer with a die area and a scribe area, and the semiconductor wafer includes a die and a testing circuit. The die is formed on the die region of the semiconductor wafer, and the die includes a main circuit. The testing circuit is disposed on the scribe area of the semiconductor wafer, and is electrically connected to the die for testing the main circuit.Type: ApplicationFiled: February 12, 2014Publication date: August 13, 2015Applicant: Winbond Electronics Corp.Inventors: Hsi-Hsien HUNG, Johnny CHAN, Dennis CHENG
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Patent number: 9013930Abstract: A method includes steps of: providing a first memory cell array including a plurality of first word lines, wherein a plurality of first data are stored in the first memory cell array; providing a second memory cell array including a plurality of second word lines, wherein the second memory cell array is separated from the first memory cell array, and a plurality of second data are stored in the second memory cell array; selecting one of the first word lines and one of the second word lines at a same time or an overlapping time; alternately selecting a first address of the first memory cell array and a second address of the second memory cell array to alternately read a first corresponding portion of the first data and a second corresponding portion of the second data from the first memory cell array and the second memory cell array.Type: GrantFiled: December 20, 2012Date of Patent: April 21, 2015Assignee: Winbond Electronics Corp.Inventors: Johnny Chan, Teng Su
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Patent number: 8953384Abstract: A sense amplifier has a reference cell current branch in which a reference cell determines a reference cell current, a column load converts the reference cell current to a reference voltage, and a feedback circuit to maintain the reference cell drain voltage. The sense amplifier also has a main cell current branch in which a main cell operationally selected from an array of flash memory cells determines a main cell current, a column load converts the main cell current to a main voltage, and a feedback circuit to maintain the main cell drain voltage. A differential amplifier compares the reference voltage with the main voltage and furnishes a logical level at its output depending on the relative values. A boost circuit has a pull up section coupled across the column load and a pull down section coupled across the main cell for accelerating the logical zero sensing time.Type: GrantFiled: July 31, 2012Date of Patent: February 10, 2015Assignee: Winbond Electronics CorporationInventors: Johnny Chan, Koying Huang
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Publication number: 20140282497Abstract: In an embodiment, a method comprises transmitting, from a mobile computing device to a server computer, first data identifying a selection at the mobile computing device of an app that is not associated with an identification module associated with the server computer that would allow the server computer to identify the device; receiving, at the mobile computing device from the server computer, second data identifying zero or more apps lacking the identification module that have been selected previously using the mobile computing device; determining whether a protocol handler for each of the zero or more apps lacking the identification module is in the mobile computing device; in response to determining that a particular protocol handler for one of the apps is in the mobile computing device, transmitting to the server computer a message specifying that the particular protocol handler is in the mobile computing device; communicating a reward to any of: a particular one of the apps that is associated with the pType: ApplicationFiled: March 12, 2014Publication date: September 18, 2014Inventors: CHRISTOPHER PAUL FARM, BRIAN STEBAR, JOHNNY CHAN, STEVE TAN