Abstract: A method of erasing a target erase area of a non-volatile memory is provided, wherein the non-volatile memory is divided into an target erase area and an unselected area, and the method includes the steps in an erase cycle of: conditioning the target erase area of the non-volatile memory, wherein the unselected area is an area, excluding the target erase area, in the non-volatile memory; erasing target cells of the target erase area, wherein the threshold of the target cells is not greater than an erase verify voltage; soft-programming the target cells, wherein the threshold of the target cells is not less than a soft program verify voltage, wherein the soft program verify voltage is less than the erase verify voltage; and refreshing a predefined portion of the unselected area, wherein the predefined portion in the erase cycle is less than the unselected area.

Abstract: A method includes steps of: providing a first memory cell array including a plurality of first word lines, wherein a plurality of first data are stored in the first memory cell array; providing a second memory cell array including a plurality of second word lines, wherein the second memory cell array is separated from the first memory cell array, and a plurality of second data are stored in the second memory cell array; selecting one of the first word lines and one of the second word lines at a same time or an overlapping time; alternately selecting a first address of the first memory cell array and a second address of the second memory cell array to alternately read a first corresponding portion of the first data and a second corresponding portion of the second data from the first memory cell array and the second memory cell array.

Abstract: A data storage device having a non-volatile memory and a controller and a control method for the non-volatile memory are disclosed. The non-volatile memory has a plurality of blocks for data storage and each block provides a plurality of sectors. The controller allocates erase marker bits in each of the sectors to record the progress of an erase operation performed on the non-volatile memory for resumption of the erase operation when required.

Abstract: A data storage device having a non-volatile memory and a controller and a control method for the non-volatile memory are disclosed. The non-volatile memory has a plurality of blocks for data storage and each block provides a plurality of sectors. The controller allocates erase marker bits in each of the sectors to record the progress of an erase operation performed on the non-volatile memory for resumption of the erase operation when required.

Abstract: A sense amplifier has a reference cell current branch in which a reference cell determines a reference cell current, a column load converts the reference cell current to a reference voltage, and a feedback circuit to maintain the reference cell drain voltage. The sense amplifier also has a main cell current branch in which a main cell operationally selected from an array of flash memory cells determines a main cell current, a column load converts the main cell current to a main voltage, and a feedback circuit to maintain the main cell drain voltage. A differential amplifier compares the reference voltage with the main voltage and furnishes a logical level at its output depending on the relative values. A boost circuit has a pull up section coupled across the column load and a pull down section coupled across the main cell for accelerating the logical zero sensing time.

Abstract: The timing of logic read operations in a Flash memory device may be improved by a pad serial output circuit which receives a pre-decoded instruction signal and pre-fetched logic data prior to the last command clock, and which performs a fast resolution of the command in the pad serial output circuit on the last clock of the command input sequence. In one illustratively implementation, instruction pre-decode and data pre-fetch may be done on the seventh clock during command input. In another illustrative implementation, a first instruction pre-decode and data pre-fetch may be done on the fourth clock during command input, and a second instruction pre-decode may be done on the seventh clock during command input. Both serial protocol interface, including dual and quad I/O SPI, and quad peripheral interface are supported.

Abstract: The timing of logic read operations in a Flash memory device may be improved by a pad serial output circuit which receives a pre-decoded instruction signal and pre-fetched logic data prior to the last command clock, and which performs a fast resolution of the command in the pad serial output circuit on the last clock of the command input sequence. In one illustratively implementation, instruction pre-decode and data pre-fetch may be done on the seventh clock during command input. In another illustrative implementation, a first instruction pre-decode and data pre-fetch may be done on the fourth clock during command input, and a second instruction pre-decode may be done on the seventh clock during command input. Both serial protocol interface, including dual and quad I/O SPI, and quad peripheral interface are supported.

Abstract: A system and method for tracking performance of an action in an application is disclosed in which a link to perform the application action is transmitted to a client device. In response to receiving an indication of the selection of the link, the performance of the action in the application by the client device is detected. Based on the detected performance of the application action, reward data is associated with a user of the client device.

Abstract: Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg of the latch and ground to limit leakage current. A large number of latches are connected in parallel and their accumulated leakage currents are limited by the switching circuit to prevent overload of a high-voltage generator, such as a charge pump circuit, for the high-voltage latch, so that data can be properly written in the memory cells of the non-volatile memory.

Abstract: A method of testing power-on reset circuitry in an integrated circuit comprises establishing the a first state of the integrated circuit that is different from a normal reset state of the circuit, lowering the VCC power supply voltage from a normal high operating level VH to a specified lower level VP then raising it back to the normal high level, then determining whether or not the integrated circuit has assumed the reset state. The testing can repeated with a plurality of lower VCC levels VP and under a variety of operating conditions to characterize resetting parameters and to designate pass/fail results for individual chips. If an AC voltage detector is part of the power-on reset circuitry, then it can tested separately, and DC testing occurs with very slow ramp rates for lowering and raising the power supply voltage.

Abstract: Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.

Abstract: A voltage generator has a control circuit for controlling a dual-mode charge pump that has multiple control options provided by an optional pull down control signal and an optional stop control signal. The dual-mode charge pump is enabled by a high voltage enable control signal from a control circuit to provide a high-voltage output voltage level Vpp or a low-voltage output voltage level Vdd. A current sink transistor is coupled from the output of the dual-mode charge pump to a ground reference through a current sink control switch transistor that is turned on by the optional pull down control signal. A dual output op amp compares a fixed voltage reference to a voltage proportional to the output voltage of the charge pump. The op amp has a high voltage output signal terminal that turns on the current sink transistor and a low voltage output signal that is coupled to the control circuit.

Abstract: A voltage generator has a control circuit for controlling a dual-mode charge pump that has multiple control options provided by an optional pull down control signal and an optional stop control signal. The dual-mode charge pump is enabled by a high voltage enable control signal from a control circuit to provide a thigh-voltage output voltage level Vpp or a low-voltage output voltage level Vdd. A current sink transistor is coupled from the output of the dual-mode charge pump to a ground reference through a current sink control switch transistor that is turned on by the optional pull down control signal. A dual output op amp compared a fixed voltage reference to a voltage proportional to the output voltage of the charge pump. The op amp has a high voltage output signal terminal that turns on the current sink transistor and a low voltage output signal that is coupled to the control circuit.

Abstract: An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg of the latch and ground to limit leakage current. A large number of latches are connected in parallel and their accumulated leakage currents are limited by the switching circuit to prevent overload of a high-voltage generator, such as a charge pump circuit, for the high-voltage latch, so that data can be properly written in the memory cells of the non-volatile memory.