Abstract: A system and method for supporting sequential burst counts of particular utility with respect to double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) devices wherein each memory bank is divided into halves, corresponding to Even (AOc=0) and Odd (AOc=1) portions. Separate address busses may be provided for those bits necessary to accommodate the maximum burst length. As the column addresses are loaded, the buffers associated with the Even bus check to determine if the pad address “Y” or “Y+1” should be loaded. Loading “Y+1” is necessary to support sequential counting if the start address is Odd (AOc=1). “Y” selects in the Odd and Even banks are then selected and incremented, concurrently. Nevertheless, the Even field is always “Y+1”, that is, YEven=YOdd+1.

Abstract: A system and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line such as those used in delay-locked loop (“DLL”) circuits in integrated circuit (“IC”) devices such as double data rate (“DDR”) dynamic random access memory (“DRAM”), static random access memory (“SRAM”), processors and other IC devices. The technique renders the incremental changes for each correction to the control voltages to the voltage controlled delay line a function of the control voltage itself. The change in the control voltage becomes smaller as the control voltage gets lower thereby effectively precluding over-correction and excessive jitter.

Abstract: An integrated circuit memory device including at least one memory bank with the memory bank being logically partitioned into even and odd portions thereof. Even and odd data buses are provided which are selectively couplable to the even and odd portions of the memory banks respectively for placing read data thereon by means of corresponding first multiplexers in response to a first control signal. A read pipeline sorting block is coupled to the even and odd data buses for selectively applying the read data on the even data bus to either of a rising or falling edge data output bus and the read data on the odd data bus to an opposite one of the rising or falling edge data output buses.

Abstract: A high speed output enable path and method for an integrated circuit device which effectively minimizes the gate delays in the critical integrated circuit device data and clock paths and in which most amplification is added in the reset path which is not critical to access time. Based on an external clock, several “one-shot” internal output enable clocks are generated. These parallel output enable clocks have select information embedded in them to facilitate the multiplexing of several different data paths onto a single output buffer. This select information is implemented ir the reset portion of the one-shot circuit thereby removing it from the critical portion for determining access time.

Abstract: A technique for integrating an internal clock signal with various function commands in an integrated circuit device having an externally supplied clock signal to create a set of command clocks which have the same rising (or falling) edge time, duty cycle and duration and are, therefore, inherently clocked to ameliorate signal “race” and “skew” conditions encountered in prior designs. The technique of the present invention, therefore, improves overall device operational speeds in executing commands by reducing internal gate delays and resulting in faster data access times in integrated circuit memory devices such as synchronous dynamic random access memory (“SDRAM”) devices. Moreover, because the resultant design provides faster operation times, lower cost process technologies may be utilized to achieve substantially comparable performance levels.

Abstract: A current sensing differential amplifier with high rejection of power supply variations and method for an integrated circuit memory device which allows the amplifier's differential voltage level and speed to track that of the sense amplifier supplying the information, thereby achieving the needed margin for critical synchronous timing. The reliability of the differential amplifier is also increased due to the provision of a larger differential signal and higher supply voltage levels. In a preferred embodiment, an n-channel transistor serves as a regulator with its drain terminal coupled to an unregulated supply voltage source ("V.sub.cc "). The gate of the transistor is then coupled to a regulated supply voltage ("V.sub.ccp ") which is a function of the voltage supply for the sense amplifier. The source of the transistor is connected to the sources of the p-channel transistors in the main amplifier which provide feedback to the main amplifier.

Abstract: A latch-up protector, and an associated method, for an electronic circuit powered by both a fixed power supply and a pumped power supply. Operation of the latch-up protector prevents the occurrence of latch-up of the circuit during powering-up of the circuit. During powering-up of the electronic circuit, the latch-up protector prevents the application of an input signal to the electronic circuit which might instigate the occurrence of latch-up until the pumped power supply reaches a selected voltage level.

Abstract: An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.

Abstract: A configurable input device for an integrated circuit having a plurality of input pads, the input device including a plurality of buffers, where each buffer is associated with one of the input pads. Each buffer receives a mode select signal and the buffer is responsive to the mode select signal to place the buffer in an enabled mode or a disabled mode. A receiver portion within each buffer is coupled to the associated input pad. The receiver portion pulls the associated input pad to a preselected logic state while the buffer is in the disabled mode. An output driver within each buffer generates an output signal responsive to a signal on the associated input pad while the buffer is in the enable mode and provides a high impedance while the buffer is in the disabled mode. An output node is coupled to the output drivers of the plurality of buffers.

Abstract: An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.