Patents by Inventor Jon C. R. Bennett

Jon C. R. Bennett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960743
    Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: April 16, 2024
    Assignee: INNOVATIONS IN MEMORY LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 11599285
    Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: March 7, 2023
    Assignee: Innovations In Memory LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 11010076
    Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: May 18, 2021
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 10761766
    Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 1, 2020
    Assignee: VIOLIN MEMORY LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 10754769
    Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 25, 2020
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 10417159
    Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: September 17, 2019
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 10372366
    Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: August 6, 2019
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 10204042
    Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: February 12, 2019
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 10176861
    Abstract: A memory system is described, where a plurality of memory modules is connected to a memory controller. Erase operations of the memory modules are coordinated by the memory controller such that, when data is stored in a group of memory modules configured to be a RAID (Redundant Array of Independent “Disks”) group, erase or refresh operations performed on the memory modules of the RAID group are synchronized, scheduled, or controlled to reduce the latency in reading the data stored on the RAID modules.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: January 8, 2019
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Publication number: 20180373627
    Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.
    Type: Application
    Filed: August 1, 2018
    Publication date: December 27, 2018
    Applicant: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. BENNETT
  • Patent number: 10157016
    Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: December 18, 2018
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 9838045
    Abstract: A system and method for storing compressed data in a memory system includes identifying user data to be compressed and compressing pages of user data to form data extents that are less than or equal to the uncompressed data. A plurality of compressed pages are combined to a least fill a page of the memory. The data may be stored as sectors of a page, where each sector includes a CRC or error correcting code for the compressed data of that sector. The stored data may also include error correcting code data for the uncompressed page and error correcting code for the compressed page. When data is read in response to a user request, the sector data is validated using the CRC prior to selecting the data from the read sectors for decompression, and the error correcting code for the uncompressed page may be used to validate the decompressed data.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 5, 2017
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 9753674
    Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 5, 2017
    Assignee: VIOLIN MEMORY INC.
    Inventors: Jon C. R. Bennett, David M. Smith, Daniel C. Biederman
  • Patent number: 9727263
    Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: August 8, 2017
    Assignee: VIOLIN MEMORY, INC.
    Inventor: Jon C. R. Bennett
  • Patent number: 9632870
    Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: April 25, 2017
    Assignee: Violin Memory, Inc.
    Inventor: Jon C. R. Bennett
  • Patent number: 9582449
    Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: February 28, 2017
    Assignee: Violin Memory, Inc.
    Inventor: Jon C. R. Bennett
  • Patent number: 9547588
    Abstract: Flash memory is subject to a wear out failure mechanism which may depend on the number of times each cell of the memory is programmed and erased. The higher the programming voltage used, the more rapidly the cell degrades. A system and method for reducing the average programming voltage for data sets is disclosed.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: January 17, 2017
    Assignee: VIOLIN MEMORY INC.
    Inventors: Daniel C. Biederman, Jon C. R. Bennett
  • Patent number: 9513845
    Abstract: A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 6, 2016
    Assignee: VIOLIN MEMORY INC.
    Inventors: Jon C. R. Bennett, Daniel C. Biederman
  • Patent number: 9495110
    Abstract: A system and method is described for operating a computer memory system having a plurality of controllers capable of accessing a common set of memory modules. Access to the physical storage of the memory modules may be managed by configuration logical units (LUNs) addressable by the users. The amount of memory associated with each LUN may be managed in units of memory (LMA) from a same free LMA table maintained in each controller of the plurality of controllers. A request for maintenance of a LUN may be received from any user through any controller and results in the association of a free memory area with the LUN, and the remaining controllers perform the same operation. A test for misallocation of a free memory area is performed and when such misallocation occurs, the situation is corrected in accordance with a policy.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 15, 2016
    Assignee: VIOLIN MEMORY, INC.
    Inventor: Jon C. R. Bennett
  • Patent number: 9465756
    Abstract: An interconnection system, apparatus and method is described where the motherboard may be populated with less than all of the modules that it has been designed to accept while maintaining a configuration such that in the event of a module failure, a memory controller failure, or a combination thereof, the connectivity of the remaining modules is maintained. Where data is stored using a RAID organization of the memory on the modules, the data may be reconstructed to a spare module. The system also provides for the orderly incremental expansion of the memory by adding additional memory modules and memory controllers, while maintaining the connectivity properties.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: October 11, 2016
    Assignee: VIOLIN MEMORY INC.
    Inventor: Jon C. R. Bennett