Abstract: An interconnection system, apparatus and method is described where the motherboard may be populated with less than all of the modules that it has been designed to accept while maintaining a configuration such that in the event of a module failure, a memory controller failure, or a combination thereof, the connectivity of the remaining modules is maintained. Where data is stored using a RAID organization of the memory on the modules, the data may be reconstructed to a spare module. The system also provides for the orderly incremental expansion of the memory by adding additional memory modules and memory controllers, while maintaining the connectivity properties.

Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.

Abstract: A system for hierarchically storing packetized data and transferring the packetized data includes an input configured to receive packets of data, a memory coupled to the input and configured to store packets of data, an output coupled to the memory and configured to transfer packets of data from the memory, and a controller coupled to the memory and configured to control the memory to store packets of data in queues associated with a hierarchy in which a first level of the hierarchy includes a group of queue group components, wherein at least one of the queue group components in the group at the first level includes a group of queue group components associated with a second level of the hierarchy that is different from the first level of the hierarchy.

Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.

Abstract: A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.

Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A memory circuit card is described, where the electrical and physical interface between the circuit card and a motherboard bus is independent of the memory type installed on the circuit card. The power supply voltage provided by the mother board is independent of the memory type, and persistent and non-persistent memory types may be used on a plurality of circuit cards installed on the motherboard. The power status of at least portions of the interfaces of the circuit card may be controlled at a future time based on signals received at an input of circuit card.

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Abstract: A system for hierarchically storing packetized data and transferring the packetized data includes an input configured to receive packets of data, a memory coupled to the input and configured to store packets of data, an output coupled to the memory and configured to transfer packets of data from the memory, and a controller coupled to the memory and configured to control the memory to store packets of data in queues associated with a hierarchy in which a first level of the hierarchy includes a group of queue group components, wherein at least one of the queue group components in the group at the first level includes a group of queue group components associated with a second level of the hierarchy that is different from the first level of the hierarchy.

Abstract: The present invention pertains to an apparatus for providing service to entities. Also, the apparatus comprises a scheduler for dynamically scheduling when the first and second entities receive service from the server. The scheduler comprises a controller which chooses entities to receive service by the server based on a weighting factor corresponding with an entity. The controller dynamically changes the weighting factor corresponding with the entity as a function of a desired condition and time. The present invention, also, pertains to a method for serving entities. The method comprises the steps of providing service to a first entity by a server at a first rate based on a first weighting factor corresponding to the first entity during a first time period. Next there is the step of providing service to a second entity by the server at a second rate based on a second weighting factor corresponding to the second entity during the first time period.

Abstract: A telecommunications switch. The switch includes a first output port mechanism through which sessions having cells are sent at a total session rate to a network. The switch includes a first input port mechanism through which sessions are received from the network. The first input port mechanism is connected to the first output port mechanism. The first input port mechanism has a first guaranteed session rate. The switch includes a second input port mechanism through which sessions are received from the network. The second input port mechanism is connected to the first output port mechanism. The second input port mechanism has a second guaranteed session rate, the sum of all guaranteed session rates are less than or equal to the total session rate. The switch includes a first scheduler connected to the first and second input port mechanisms and to the first output port mechanism for scheduling sessions of the input port mechanisms for service.

Abstract: The present invention pertains to a multicast system. The system comprises an ATM network. The system comprises a source connected to the ATM network. The system also comprises a first destination connected to the ATM network. The system comprises at least a second destination connected to the ATM network. Additionally, the system comprises a mechanism for adding or dropping connections dynamically between the first source and any destinations at any time. The present invention pertains to a method for multicasting ATM cells. The method comprises the steps of forming a first connection between a first source and a first destination for transmitting a first ATM cell therebetween. Next, there is be step of forming a second connection between the first source and a second destination while the first connection exists. Then there is the step of terminating the first connection while the second connection exists. The present invention pertains to a method for multicasting ATM cells.

Abstract: The present invention pertains to a multicast system. The system comprises an ATM network. The system comprises a source connected to the ATM network. The system also comprises a first destination connected to the ATM network. The system comprises at least a second destination connected to the ATM network. Additionally, the system comprises a mechanism for adding or dropping connections dynamically between the first source and any destinations at any time. The present invention pertains to a method for multicasting ATM cells. The method comprises the steps of forming a first connection between a first source and a first destination for transmitting a first ATM cell therebetween. Next, there is be step of forming a second connection between the first source and a second destination while the first connection exists. Then there is the step of terminating the first connection while the second connection exists. The present invention pertains to a method for multicasting ATM cells.

Abstract: A scheduler for a server for serving ATM cells. The scheduler includes R rate bins where R is greater than or equal to 2. The scheduler includes a controller which places a session having a desired rate into a rate bin of the R rate bins. A system for transmitting ATM cells. The system includes an ATM network along which ATM cells are transmitted. The system includes S sources where S is greater than or equal to 1 and is an integer. Each source is connected to the network and produces ATM cells for transmission on the network. The system includes D destinations where D is greater than or equal to 1 and is an integer. Each destination is connected to the network. Each destination receives ATM cells from the network. The system includes a server connected to the ATM network. Additionally, the system includes a scheduler which has R different rate bins for holding sessions, where R is an integer greater than or equal to 2.

Abstract: The present invention pertains to an apparatus for providing service to entities. The apparatus comprises a server for providing the service. The apparatus also comprises a plurality of entities which require the service of the server. The entities are connected with the server. Additionally, the apparatus comprises a scheduler for scheduling when each of the entities receives the service of the server. The scheduler is connected with the server and the entities. There is a time stamp mechanism for providing a longer-format time stamp to a requesting entity of the plurality of entities whenever the requesting entity requests service from the server. The time stamp mechanism is connected to the scheduler and the server. Moreover, the apparatus comprises means for compressing the longer-format time stamp into a corresponding shorter-format window-based time stamp and storing the shorter-format window based time stamp.

Abstract: A system and method of generating flow control information for a switching node for a digital network is disclosed. The network includes a source device and a destination device interconnected by the switching node. The source device generates cells for transmission at a selected transmission rate to the destination device over a path through the switching node to transmit data in a downstream direction from the source device to the destination device. The source device further periodically generates resource management cells for transmission to the destination device over the path in the downstream direction, and the destination device returns the resource management cells over the path in upstream direction through the switching node to the source device.

Abstract: The present invention pertains to a method for multicasting ATM cells. The method comprises the steps of reading a first ATM cell to which a first cell read pointer is pointing. Then there is the step of transmitting the first ATM cell out a first port to a first address. Next there is the step of determining whether the first ATM cell is to be transmitted out the first port to a second address. Next there is the step of reading a cell pointer pointing to a second ATM cell if the transmission of the first ATM cell out the first port to addresses is completed. The present invention pertains to a multicast system for an ATM network. The multicast system is comprised of a first ATM cell pointer mechanism associated with a first port. The multicast system also comprises at least a second ATM cell pointer mechanism associated with a second port. The multicast system is also comprised of at least a first ATM cell.