Abstract: A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

Abstract: A semiconductor device comprising a substrate having a first crystal orientation is provided. A first insulating layer overlies the substrate and a plurality of silicon layers overlie the first insulating layer. A first silicon layer comprises silicon having a second crystal orientation and a crystal plane. A second silicon layer comprises silicon having the second crystal orientation and a crystal plane that is substantially orthogonal to the crystal plane of the first silicon layer. Because holes have higher mobility in the (110) plane than the (100) plane, while electrons have higher mobility in (100) plane than the (110) plane, semiconductor device performance can be enhanced by the selection of silicon layers with certain crystal plane orientations. In addition, a method of forming a semiconductor device is provided.

Abstract: A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode (207) disposed on a substrate (203); (b) creating first (213) and second (214) pre-amorphization implant regions in the substrate such that the first and second pre-amorphization implant regions are asymmetrically disposed with respect to said gate electrode; (c) creating first (219) and second (220) spacer structures adjacent to first and second sides of the gate electrode, wherein the first and second spacer structures overlap the first and second pre-amorphization implant regions; and (d) creating source (217) and drain (218) regions in the substrate adjacent, respectively, to the first and second spacer structures.

Abstract: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

Abstract: A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.

Abstract: STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 ?. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.

Abstract: A resistive structure formed overlying a semiconductor substrate is masked with a silicide block layer to define a portion of the resistive structure that is to be unsilicided and a portion of the resistive structure to be silicided. The silicide block layer is changed to facilitate different processes.

Abstract: The present invention is generally directed to various methods of forming metal silicide regions on transistors based upon gate critical dimensions. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a plurality of transistors, reducing a thickness of at least a portion of the layer of refractory metal above at least some of the transistors and performing at least one anneal process to form metal silicide regions above the transistors. In another illustrative embodiment, the method comprises forming a layer of refractory metal above the plurality of transistors, reducing the thickness of the layer of refractory metal above a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, and performing at least one anneal process to form metal silicide regions on the plurality of transistors.

Abstract: A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, forming source/drain regions in the substrate adjacent the gate electrode by performing at least the following steps: performing two ion implantation processes to form source/drain extensions for the device and performing a third ion implantation process to further form source/drain regions for the device. Various N-type and P-type dopant atoms such as arsenic, phosphorous, boron and boron difluoride may be used with the present invention.

Abstract: The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining a recess thereabove, a gate electrode and a gate insulation layer positioned above the substrate, a portion of the gate electrode and the gate insulation layer extending into the recess above the recessed isolation structure, and a source region and a drain region formed in the substrate. In another illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure that defines an active area having an upper surface and an exposed sidewall surface, a gate insulation layer and a gate electrode positioned above a portion of the upper surface and a portion of the exposed sidewall surface of the active area, and a source region and a drain region formed in the active area.

Abstract: Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type.

Abstract: In one illustrative embodiment, the method comprises forming a sacrificial layer of material above a substrate comprised of silicon, performing a wet etching process to remove the sacrificial layer, implanting fluorine atoms into selected portions of the substrate after the sacrificial layer is removed, and performing a thermal oxidation process to form a plurality of gate insulation layers above the substrate, the gate insulation layers formed above the fluorine implanted selected portions of the substrate having a thickness that is greater than a thickness of the gate insulation layers formed above portions of the substrate not implanted with fluorine.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.

Abstract: A transistor, comprising a semiconducting substrate, a gate insulation layer positioned above the substrate, a gate electrode positioned above the gate insulation layer, a plurality of source/drain regions formed in the substrate, a first and a second sidewall spacer positioned adjacent the gate electrode, and a metal silicide layer formed above each of the source/drain regions, a portion of the metal silicide layer being positioned adjacent the first sidewall spacer and under the second sidewall spacer.

Abstract: The present invention is directed to a method that comprises forming a plurality of transistors, each transistor having at least a gate electrode, and forming halo implant regions in the transistors while varying at least one of a halo implant angle, a masking layer height, and a lateral offset of a masking layer from the gate electrode of the transistors. The method further comprises determining electrical performance characteristics of at least some of the transistors where at least one of the halo implant angle, the masking layer height, and the lateral offset of a masking layer are different, and comparing the determined electrical performance characteristics of the transistors.

Abstract: The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implant process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.