INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT
An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.
Latest FREESCALE SEMICONDUCTOR, INC. Patents:
- AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF
- METHODS AND SYSTEMS FOR ELECTRICALLY CALIBRATING TRANSDUCERS
- SINTERED MULTILAYER HEAT SINKS FOR MICROELECTRONIC PACKAGES AND METHODS FOR THE PRODUCTION THEREOF
- CONTROLLED PULSE GENERATION METHODS AND APPARATUSES FOR EVALUATING STICTION IN MICROELECTROMECHANICAL SYSTEMS DEVICES
- SYSTEMS AND METHODS FOR CREATING BLOCK CONSTRAINTS IN INTEGRATED CIRCUIT DESIGNS
This invention relates to integrated circuits, and more particularly to integrated circuits that have an interlayer dielectric that is stressed to improve performance of the integrated circuits.
BACKGROUND OF THE INVENTIONOne of the techniques that has been under development to improve transistor mobility is strained silicon. Typically the silicon layer is put under tensile stress to improve the N channel mobility. This has been extended to using an interlayer dielectric (ILD), a dielectric layer between conductive layers, that is under a selected stress to improve transistor performance. For N channel transistors this has meant using tensile stress, and for P channel transistors this has meant using compressive stress.
The foregoing and further and more specific objects and advantages of the invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the following drawings:
In one aspect an integrated circuit that has both logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and N channel SRAM transistors both have ILDs with non-compressive stress, the P channel transistor ILD has compressive stress, and the P channel SRAM transistors at least have less compressive stress than the P channel logic transistors, i.e., the P channel SRAM transistors may be compressive but with less magnitude of such compressive stress than the logic P channel transistors, may be relaxed, or may be tensile. It has been found to be advantageous for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage. This is better understood by reference to the drawings and the following description.
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Shown in
Various changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. For example, the order of formation of dielectric layers can be changed. Instead of forming tensile layer 40 first, compressive layer 42 could be formed first. Also these embodiments have been shown using an SOI substrate but another substrate type, such as bulk or bulk-SOI hybrid, could also be used. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.
Claims
1-17. (canceled)
18. A method of making a semiconductor device comprising:
- forming a first N channel transistor that is used in a logic circuit;
- forming a first P channel transistor that is used in the logic circuit;
- forming a second N channel transistor that is used in a SRAM array;
- forming a second P channel transistor that is used in the SRAM array;
- depositing a first dielectric layer over the semiconductor device that has a first stress;
- removing the first dielectric layer over the first and second P channel transistors;
- depositing a second dielectric layer over the semiconductor device that has a second stress that is more compressive than the first stress; and
- removing the second layer over the first and second N channel transistors and the second P channel transistor;
- depositing a third dielectric layer over the semiconductor device that has a third stress that is between the first stress and the second stress;
- removing the third dielectric layer over the first and second N channel transistors and the first P channel transistor.
19. A method of making a semiconductor device comprising:
- forming a first N channel transistor that is used in a logic circuit;
- forming a first P channel transistor that is used in the logic circuit;
- forming a second N channel transistor that is used in a SRAM array;
- forming a second P channel transistor that is used in the SRAM array;
- depositing a first dielectric layer over the semiconductor device that has a first stress;
- removing the first dielectric layer over the first and second P channel transistors;
- depositing a second dielectric layer over the semiconductor device that has a second stress that is more compressive than the first stress; and
- removing the second dielectric layer over the first and second N channel transistors whereby a first portion of the second dielectric layer is left on the first P channel transistor and a second portion of the second dielectric layer is left over the second P channel transistor; and
- implanting into the second portion of the second dielectric layer to cause the second portion of the second dielectric layer to become less compressive.
20. A method of making a semiconductor device, comprising:
- forming a first portion comprising a first transistor of the first type and a first transistor of a second type for use in a circuit of a first type;
- forming a second portion comprising a second transistor of the first type and a second transistor of the second type for use in a circuit of a second type;
- forming a first ILD over the first transistor of the first type having a first stress of a first type; and
- forming a second ILD over the second transistor of the first type having a second stress that is at least less than the first stress of the first type.
Type: Application
Filed: Apr 1, 2010
Publication Date: Jul 29, 2010
Applicant: FREESCALE SEMICONDUCTOR, INC. (Austin, TX)
Inventors: James D. Burnett (Austin, TX), Jon D. Cheek (Cedar Park, TX)
Application Number: 12/752,699
International Classification: H01L 21/31 (20060101);