Patents by Inventor Jon-Hsu Ho
Jon-Hsu Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9711596Abstract: A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed.Type: GrantFiled: December 2, 2014Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hao-Ling Tang, Jon-Hsu Ho, Shao-Hwang Sia, Wen-Hsing Hsieh, Ching-Wei Tsai
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Patent number: 9620500Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: GrantFiled: May 18, 2016Date of Patent: April 11, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chi Wang, Chien-Chih Lee, Tien-Wei Chiang, Ching-Wei Tsai, Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh
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Patent number: 9502409Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: GrantFiled: February 18, 2015Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Chih Chieh Yeh, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20160260713Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: ApplicationFiled: May 18, 2016Publication date: September 8, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chi WANG, Chien-Chih LEE, Tien-Wei CHIANG, Ching-Wei TSAI, Chih-Ching WANG, Jon-Hsu HO, Wen-Hsing HSIEH
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Patent number: 9373620Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: GrantFiled: September 12, 2014Date of Patent: June 21, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chi Wang, Chien-Chih Lee, Tien-Wei Chiang, Ching-Wei Tsai, Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh
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Patent number: 9318322Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: GrantFiled: November 13, 2014Date of Patent: April 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Publication number: 20160079239Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Chin-Chi WANG, Chien-Chih LEE, Tien-Wei CHIANG, Ching-Wei TSAI, Chih-Ching WANG, Jon-Hsu HO, Wen-Hsing HSIEH
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Publication number: 20150372083Abstract: A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed.Type: ApplicationFiled: December 2, 2014Publication date: December 24, 2015Inventors: HAO-LING TANG, JON-HSU HO, SHAO-HWANG SIA, WEN-HSING HSIEH, CHING-WEI TSAI
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Publication number: 20150162334Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: ApplicationFiled: February 18, 2015Publication date: June 11, 2015Inventors: Jon-Hsu HO, Chih-Ching WANG, Ching-Fang HUANG, Wen-Hsing HSIEH, Tsung-Hsing YU, Yi-Ming SHEU, Chih-Chieh YEH, Ken-Ichi GOTO, Zhiqiang WU
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Patent number: 8987824Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: GrantFiled: November 22, 2011Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Chih-Chieh Yeh, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20150079752Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: ApplicationFiled: November 13, 2014Publication date: March 19, 2015Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Patent number: 8981479Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: GrantFiled: December 17, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Patent number: 8890207Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: GrantFiled: December 22, 2011Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
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Patent number: 8765533Abstract: A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin.Type: GrantFiled: December 4, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsing Hsieh, Zhiqiang Wu, Ching-Fang Huang, Jon-Hsu Ho
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Publication number: 20140103438Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching WANG, Jon-Hsu HO, Ching-Fang HUANG, Wen-Hsing HSIEH, Tsung-Hsing YU, Yi-Ming SHEU, Ken-Ichi GOTO, Zhiqiang WU
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Patent number: 8623716Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: GrantFiled: November 3, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20130126981Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jon-Hsu HO, Chih-Ching WANG, Ching-Fang HUANG, Wen-Hsing HSIEH, Tsung-Hsing YU, Yi-Ming SHEU, Chih-Chieh YEH, Ken-Ichi GOTO, Zhiqiang WU
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Publication number: 20130113042Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.Type: ApplicationFiled: November 3, 2011Publication date: May 9, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ching Wang, Jon-Hsu Ho, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20130056795Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: ApplicationFiled: December 22, 2011Publication date: March 7, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang