Patents by Inventor Jon K. Kriegel
Jon K. Kriegel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8490110Abstract: Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.Type: GrantFiled: February 15, 2008Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Russell D. Hoover, Jon K. Kriegel, Eric O. Mejdrich, Robert A. Shearer
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Patent number: 8438578Abstract: Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.Type: GrantFiled: June 9, 2008Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Russell D. Hoover, Jon K. Kriegel, Eric O. Mejdrich
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Patent number: 8429377Abstract: A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.Type: GrantFiled: January 8, 2010Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Jon K. Kriegel, Martin Ohmacht, Burkhard Steinmacher-Burow
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Publication number: 20130024648Abstract: A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.Type: ApplicationFiled: September 14, 2012Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Jon K. Kriegel, Martin Ohmacht, Burkhard Steinmacher-Burow
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Publication number: 20130007408Abstract: A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.Type: ApplicationFiled: September 14, 2012Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: Hubertus Franke, Benjamin Herrenschmidt, Jon K. Kriegel, Andrew M. Theurer, James Xenidis
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Patent number: 8296547Abstract: An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.Type: GrantFiled: August 26, 2009Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Timothy H. Heil, Benjamin Herrenschmidt, Jon K. Kriegel, Paul Mackerras, Andrew H. Wottreng
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Patent number: 8275971Abstract: A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.Type: GrantFiled: August 27, 2008Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Hubertus Franke, Benjamin Herrenschmidt, Jon K. Kriegel, Andrew M. Theurer, James Xenidis
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Publication number: 20120215988Abstract: Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state.Type: ApplicationFiled: May 2, 2012Publication date: August 23, 2012Applicant: International Business Machines CorporationInventors: Jon K. Kriegel, Jamie R. Kuesel
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Patent number: 8230179Abstract: Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state.Type: GrantFiled: May 15, 2008Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Jon K. Kriegel, Jamie R. Kuesel
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Patent number: 8205067Abstract: A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread.Type: GrantFiled: January 11, 2010Date of Patent: June 19, 2012Assignee: International Business Machines CorporationInventors: Jon K. Kriegel, Eric Oliver Mejdrich
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Publication number: 20110173411Abstract: A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.Type: ApplicationFiled: January 8, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Jon K. Kriegel, Martin Ohmacht, Burkhard Steinmacher-Burow
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Patent number: 7913010Abstract: A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); each IP block adapted to the data communications bus through a memory communications controller and a bus interface controller; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between an IP block and memory; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between one of the IP blocks and other IP blocks; each IP block adapted to the data communications bus by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.Type: GrantFiled: February 15, 2008Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Russell D. Hoover, Jon K. Kriegel, Eric O. Mejdrich
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Patent number: 7840757Abstract: Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.Type: GrantFiled: July 29, 2004Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Bruce L. Beukema, Russell D. Hoover, Jon K. Kriegel, Jamie R. Kuesel, Eric O. Mejdrich, Robert A. Shearer, Bruce M. Walk
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Patent number: 7818503Abstract: One embodiment of the invention provides a method and apparatus for utilizing memory. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.Type: GrantFiled: December 7, 2006Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Russell Dean Hoover, Jon K. Kriegel, Eric Oliver Mejdrich, Robert Allen Shearer
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Patent number: 7752413Abstract: A method and apparatus for communicating between threads in a processor. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.Type: GrantFiled: December 7, 2006Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Russell Dean Hoover, Jon K. Kriegel, Eric Oliver Mejdrich, Robert Allen Shearer
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Publication number: 20100115250Abstract: A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread.Type: ApplicationFiled: January 11, 2010Publication date: May 6, 2010Applicant: International Business Machines CorporationInventors: JON K. KRIEGEL, Eric Oliver Mejdrich
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Patent number: 7681020Abstract: A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread.Type: GrantFiled: April 18, 2007Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Jon K. Kriegel, Eric Oliver Mejdrich
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Publication number: 20100058358Abstract: A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.Type: ApplicationFiled: August 27, 2008Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hubertus Franke, Benjamin Herrenschmidt, Jon K. Kriegel, Andrew M. Theurer, James Xenidis
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Publication number: 20100058026Abstract: An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.Type: ApplicationFiled: August 26, 2009Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Heil, Benjamin Herrenschmidt, Jon K. Kriegel, Paul Mackerras, Andrew H. Wottreng
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Publication number: 20090307714Abstract: Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.Type: ApplicationFiled: June 9, 2008Publication date: December 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Russell D. Hoover, Jon K. Kriegel, Eric O. Mejdrich