Abstract: Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache's state; and if the data is not cached, returning the data from main memory without affecting the write-back cache's state.

Abstract: A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); each IP block adapted to the data communications bus through a memory communications controller and a bus interface controller; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between an IP block and memory; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between one of the IP blocks and other IP blocks; each IP block adapted to the data communications bus by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.

Abstract: Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.

Abstract: Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, detect a new task priority for a processor, where the processor is connected to a first node, find a home node for the processor via a cluster to which the processor belongs, and send the new task priority to the home node if the home node is different from the first node. In another embodiment, an interrupt directed to a first processor is detected, the interrupt is determined to be redirectable, a home node for the first process is found via a cluster to which the first processor belongs, and an interrupt vector is sent to the home node if the home node is different from the first node.

Abstract: A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block.

Abstract: Exemplary embodiments of the present invention comprise a method for the utilization of entry-replacement index hint information within a software-managed TLB. The method comprises receiving an address translation request at a TLB and retrieving the address translation information from a page table in the event of a miss lookup event at the TLB. The method further comprises retrieving index replacement hint information from a hardware component, wherein the hardware component is configured to execute a predetermined replacement algorithm and writing the address translation information to a TLB index referenced within the index replacement hint information.

Abstract: According to embodiments of the invention, methods and apparatus are provided for tracking the status or state of a message spawned or sent from one processing element to another processing element in a multiple core processing element network. According to embodiments of the invention, a message status tracker may be incorporated within a multiple core processing element network. As a message is spawned or sent from an originating processing element to a receiving processing element, a counter within the message status tracker may be incremented. If the receiving processing element spawns further messages in response to the received message, the counter may be further incremented. When a receiving processing element finishes a process in response to a received message, the receiving processing element may decrement the counter. When the counter is decremented to an original value (e.g., zero) the original message may be considered complete.

Abstract: A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread.

Abstract: One embodiment of the invention provides a method and apparatus for utilizing memory. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.

Abstract: A method and apparatus for communicating between threads in a processor. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.

Abstract: Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.

Abstract: Method and apparatus for supporting interrupt devices configured for a specific architecture (e.g., APIC-based software and hardware) on a different platform (e.g., a PowerPC platform).