Patents by Inventor Jon S. Martens

Jon S. Martens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10225073
    Abstract: A system for obtaining measurements for a device under test (DUT) includes a vector network analyzer including a storage medium and a controller for controlling a sweep and a trigger driver configured to provide a synchronization signal to the DUT and the controller to synchronize internal signal components of the vector network analyzer including signal sources, local oscillators (LOs) and an analog-to-digital converter (ADC) clock. A signal is received by the vector network analyzer in response to a test signal generated and transmitted to the DUT. Data related to the received signal is acquired and stored in at the storage medium. The controller inserts a mark into the time record based on an event of the sweep for identifying data from the received signal associated with the event within the time record.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 5, 2019
    Assignee: ANRITSU COMPANY
    Inventors: Jon S. Martens, Elena Vayner, Jamie Tu
  • Patent number: 9753071
    Abstract: A method for obtaining improved resolution pulsed radio frequency (RF) measurements with phase coherence for a device under test (DUT) using a vector network analyzer (VNA) includes generating a pulsed RF test signal, transmitting the pulsed RF test signal to the DUT and receiving a signal from the DUT at the VNA in response to the pulsed RF test signal. An intermediate frequency (IF) signal is generated using a local oscillator (LO) signal. A phase of the LO signal is shifted by a prescribed amount while generating the IF signal. The IF signal is then sampled over multiple pulses and measurements are constructed from the measurements. A discrete Fourier transform (DFT) is then applied to the constructed measurements.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: September 5, 2017
    Assignee: ANRITSU COMPANY
    Inventor: Jon S. Martens
  • Patent number: 9606212
    Abstract: A method for measuring scattering parameters in a device under test (DUT) using a vector network analyzer (VNA), includes calibrating the VNA to generate corrections for deterministic setup defects and mapping a plurality of error terms based on a plurality of time indices, wherein each time indicia is associated with an error term. A test signal is transmitted to the DUT to obtain a measurement signal from the DUT in response to the test signal. The generated corrections to obtained measurements are time aligned based on the mapped error terms.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 28, 2017
    Assignee: ANRITSU COMPANY
    Inventor: Jon S. Martens
  • Patent number: 9176174
    Abstract: A system adapted to measure electrical performance of a device under test (DUT) having two or more ports includes a plurality of signal sources synchronized and configured to generated signals simultaneously, a plurality of first signal paths to obtain transmitted and reflected signals from the DUT, a plurality of second signal paths to obtain incident signals from the signal sources, and a receiver for receiving the reflected, transmitted and incident signals obtained at the first signal paths and the second signal paths. The receiver is adapted to separate the reflected and the transmitted signals obtained from each of the first signal paths. The signal sources are configured to each generate a signal having a frequency offset from each of the others of the signal sources by a known frequency delta.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 3, 2015
    Assignee: ANRITSU COMPANY
    Inventors: Donald Anthony Bradley, Karam Michael Noujeim, Jon S. Martens
  • Patent number: 9103873
    Abstract: In an embodiment, a system for measuring high frequency response of a DUT having improved power leveling includes a signal source, a modulator, an upconverter, and a leveling loop having dynamic gain adjustment. The signal source generates a test signal and the modulator modulates the amplitude of the generated test signal to target a requested power. The converter multiplies a frequency of the test signal. The leveling loop is configured to detect an intermediate frequency (IF) signal generated in response to the upconverted test signal. Modulation of the amplitude of the generated test signal by the modulator is adjustable based on the IF signal detected by the leveling loop.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: August 11, 2015
    Assignee: ANRITSU COMPANY
    Inventors: Jon S Martens, Karam M Noujeim, Thomas H Roberts, Jamie Tu
  • Patent number: 8417189
    Abstract: A high-frequency VNA system is provided using non-linear transmission line (NLTL or shockline) based samplers configured to provide scalable operation characteristics. Scaling to adjust noise performance vs. frequency is accomplished as follows: (1) increasing or decreasing the fall time of a shockline's output voltage waveform. This is accomplished by changing the number of Schottky varactors in a shockline, as well as changing the shockline's Bragg cutoff frequency by setting the spacing between Schottky varactors; (2) changing the structure of the pulse-forming network connected with the sampler by changing the length of the differentiator arms in the sampler pulse-forming network; and (3) changing the LO signal frequency applied to the shockline. Multiple NLTL based samplers are multiplexed to form a broadband reflectometer with the multiplexing circuitry selectively connecting one of the NLTL based sampler segments at a time to allow user selection of a desired performance vs.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: April 9, 2013
    Assignee: Anritsu Company
    Inventors: Karam Michael Noujeim, Jon S. Martens
  • Patent number: 8306134
    Abstract: A high speed receiver is provided using two parallel processing paths to enable rapid variable gain control. The parallel processing paths include a first processing path using a high resolution Discrete Fourier Transform (DFT), and a second processing path using a reduced DFT requiring fewer samples than the high resolution DFT. An initial sample of the data is processed using the second processing path with the reduced DFT by comparing a Fourier transform of the initial sample with predetermined threshold values. As a result of the comparison of the Fourier transform of the initial sample with the predetermined threshold values, a gain determination block determines whether a requirement exists for gain ranging. If gain ranging is needed, the gain of the data signal is adjusted and the gain ranging process repeats.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: November 6, 2012
    Assignee: Anritsu Company
    Inventors: Jon S. Martens, Helen Chau, David A. Rangel-Guzman, Peter A. Kapetanic, Dan Levassuer
  • Patent number: 8185078
    Abstract: A system and method for implementing dynamic spur avoidance in a high speed receiver environment is provided. For a plurality of radio frequency (RF) input signal ranges, a range of intermediate frequency (IF) signals and a noise floor for each IF signal is determined. An identification of spurs that will affect the noise floor is also determined from a look up table for each range of the RF inputs. A frequency plan that sets local oscillator and constituent oscillator signals is selected such that the IF signals generated from the RF input will avoid lower order spurious responses of the identified spurs within the IF signal range.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: May 22, 2012
    Assignee: Anritsu Company
    Inventors: Jon S. Martens, Oggi P. Lin, Thomas J. Albrecht, Peter A. Kapetanic
  • Publication number: 20110304318
    Abstract: A system is provided using one or more shocklines or non-linear transmission lines (NLTLs) to extend the bandwidth of an RF signal source. Extension of the RF bandwidth is achieved by means of multiplexing as well as frequency scaling. Frequency scaling tailors the performance of each NLTL for operation in a particular output frequency band(s) by adjusting the varactor spacing in the NLTL. Multiplexing amalgamates the output frequency bands of one or more NLTLs, thus resulting in a broad output frequency range.
    Type: Application
    Filed: May 5, 2011
    Publication date: December 15, 2011
    Applicant: ANRITSU COMPANY
    Inventors: Karam Michael Noujeim, Jon S. Martens
  • Publication number: 20110306314
    Abstract: A high-frequency VNA system is provided using non-linear transmission line (NLTL or shockline) based samplers configured to provide scalable operation characteristics. Scaling to adjust noise performance vs. frequency is accomplished as follows: (1) increasing or decreasing the fall time of a shockline's output voltage waveform. This is accomplished by changing the number of Schottky varactors in a shockline, as well as changing the shockline's Bragg cutoff frequency by setting the spacing between Schottky varactors; (2) changing the structure of the pulse-forming network connected with the sampler by changing the length of the differentiator arms in the sampler pulse-forming network; and (3) changing the LO signal frequency applied to the shockline. Multiple NLTL based samplers are multiplexed to form a broadband reflectometer with the multiplexing circuitry selectively connecting one of the NLTL based sampler segments at a time to allow user selection of a desired performance vs.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 15, 2011
    Applicant: ANRITSU COMPANY
    Inventors: Karam Michael Noujeim, Jon S. Martens
  • Publication number: 20110098014
    Abstract: A system and method for implementing dynamic spur avoidance in a high speed receiver environment is provided. For a plurality of radio frequency (RF) input signal ranges, a range of intermediate frequency (IF) signals and a noise floor for each IF signal is determined. An identification of spurs that will affect the noise floor is also determined from a look up table for each range of the RF inputs. A frequency plan that sets local oscillator and constituent oscillator signals is selected such that the IF signals generated from the RF input will avoid lower order spurious responses of the identified spurs within the IF signal range.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 28, 2011
    Applicant: ANRITSU COMPANY
    Inventors: Jon S. Martens, Oggi P. Lin, Thomas J. Albrecht, Peter M. Kapetanic
  • Patent number: 7924024
    Abstract: A calibration module, for use in calibrating a VNA, includes ports connectable to the VNA, calibration standards, and single pole multi throw (SPMT) switches. Each SPMT includes a single pole terminal, multiple throw terminals and a shunt terminal corresponding to each multiple throw terminal. A switching path is between each throw terminal and the single pole terminal, and between each shunt terminal and the single pole terminal. Each switching path includes at least one solid state switching element. The calibration standards are selectively connectable to the ports of the calibration module by selectively controlling the switching elements. Each port of the calibration module is directly connected to a throw terminal of one of the SPMT switches. Also, unique algorithm are provided for calibrating a VNA when using a calibration impedance that is a hybrid of a reflect standard and a transmission standard, which can be achieved using the calibration module.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: April 12, 2011
    Assignee: Anritsu Company
    Inventors: Jon S. Martens, Alexander Feldman
  • Publication number: 20110013733
    Abstract: A high speed receiver is provided using two parallel processing paths to enable rapid variable gain control. The parallel processing paths include a first processing path using a high resolution Discrete Fourier Transform (DFT), and a second processing path using a reduced DFT requiring fewer samples than the high resolution DFT. An initial sample of the data is processed using the second processing path with the reduced DFT by comparing a Fourier transform of the initial sample with predetermined threshold values. As a result of the comparison of the Fourier transform of the initial sample with the predetermined threshold values, a gain determination block determines whether a requirement exists for gain ranging. If gain ranging is needed, the gain of the data signal is adjusted and the gain ranging process repeats.
    Type: Application
    Filed: July 17, 2009
    Publication date: January 20, 2011
    Applicant: ANRITSU COMPANY
    Inventors: Jon S. Martens, Helen Chau, David A. Rangel-Guzman, Peter M. Kapetanic, Dan Levasseur
  • Patent number: 7545151
    Abstract: Provided herein are techniques for characterizing a test fixture that is used for connecting a device under test (DUT) to a vector network analyzer (VNA), e.g., to thereby enable de-embedding of the test fixture from measurements of the DUT connected to the test fixture. In an embodiment, the test fixture is separated into 4-port test fixture segments, based on which ports of the DUT have internal coupling. Each test fixture segment has an outer 2-port reference plane and an inner 2-port reference plane. A 4-port calibration is performed at outer planes of the two test fixture segments, while corresponding ports of the inner planes of the test fixture segments are connected together with thru segments, to thereby determine a thru set of S-parameters. A set of S-parameters is determined for each of the 4-port test fixture segments, based on the thru set of S-parameters.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: June 9, 2009
    Assignee: Anritsu Company
    Inventors: Jon S. Martens, David V. Judge
  • Publication number: 20080258738
    Abstract: Provided herein are techniques for characterizing a test fixture that is used for connecting a device under test (DUT) to a vector network analyzer (VNA), e.g., to thereby enable de-embedding of the test fixture from measurements of the DUT connected to the test fixture. In an embodiment, the test fixture is separated into 4-port test fixture segments, based on which ports of the DUT have internal coupling. Each test fixture segment has an outer 2-port reference plane and an inner 2-port reference plane. A 4-port calibration is performed at outer planes of the two test fixture segments, while corresponding ports of the inner planes of the test fixture segments are connected together with thru segments, to thereby determine a thru set of S-parameters. A set of S-parameters is determined for each of the 4-port test fixture segments, based on the thru set of S-parameters.
    Type: Application
    Filed: April 20, 2007
    Publication date: October 23, 2008
    Applicant: ANRITSU COMPANY
    Inventors: Jon S. Martens, David V. Judge
  • Publication number: 20080197858
    Abstract: A calibration module, for use in calibrating a VNA, includes ports connectable to the VNA, calibration standards, and single pole multi throw (SPMT) switches. Each SPMT includes a single pole terminal, multiple throw terminals and a shunt terminal corresponding to each multiple throw terminal. A switching path is between each throw terminal and the single pole terminal, and between each shunt terminal and the single pole terminal. Each switching path includes at least one solid state switching element. The calibration standards are selectively connectable to the ports of the calibration module by selectively controlling the switching elements. Each port of the calibration module is directly connected to a throw terminal of one of the SPMT switches. Also, unique algorithm are provided for calibrating a VNA when using a calibration impedance that is a hybrid of a reflect standard and a transmission standard, which can be achieved using the calibration module.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 21, 2008
    Applicant: ANRITSU COMPANY
    Inventors: Jon S. Martens, Alexander Feldman
  • Patent number: 6943563
    Abstract: An S-parameter measurement technique allows measurement of devices under test (DUTs), such as power amplifiers, which require a modulated power tone drive signal for proper biasing, in combination with a probe tone test signal, wherein both the modulated and probe tone signals operate in the same frequency range. The technique uses a stochastic drive signal, such as a CDMA or WCDMA modulated signal in combination with a low power probe tone signal. A receiver in a VNA having a significantly narrower bandwidth than the modulated signal bandwidth enables separation of the modulated and probe tone signals. VNA calibration further improves the measurement accuracy. For modulated signals with a significant power level in the frequency range of the probe tone signal, ensemble averaging of the composite probe tone and power tone signals is used to enable separation of the probe tone signal for measurement.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: September 13, 2005
    Assignee: Anritsu Company
    Inventor: Jon S. Martens
  • Patent number: 6928373
    Abstract: Methods, systems and computer program products for efficiently characterizing devices under test (DUTs) using a vector network analyzer (VNA) are provided. A N-port DUT can be divided as appropriate into multiple sub-devices, or multiple separate devices can be present. A parent calibration is performed. The VNA is then used to determine the S-parameters of interest for each sub-device or separate device, preferably without measuring S-parameters that are not of interest. This can include measuring S-parameters and removing corresponding error coefficients determined during the parent calibration.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: August 9, 2005
    Assignee: Anritsu Company
    Inventors: Jon S. Martens, Rena Ho, Jamie Tu
  • Patent number: 6882160
    Abstract: Techniques are provided for performing full N-port calibrations in an environment in which a test set is used to connect an N-port DUT to an M-port VNA, where N>M. Techniques for incorporating port impedances as part of a calibration sequence are provided. Also provided are techniques for using sequential characterization and de-embedding to generate virtual calibrations that are then used in a renormalization process.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: April 19, 2005
    Assignee: Anritsu Company
    Inventors: Jon S. Martens, David V. Judge, Jimmy A. Bigelow
  • Publication number: 20040251922
    Abstract: Techniques are provided for performing full N-port calibrations in an environment in which a test set is used to connect an N-port DUT to an M-port VNA, where N>M. Techniques for incorporating port impedances as part of a calibration sequence are provided. Also provided are techniques for using sequential characterization and de-embedding to generate virtual calibrations that are then used in a renormalization process.
    Type: Application
    Filed: November 5, 2003
    Publication date: December 16, 2004
    Applicant: Anritsu Company
    Inventors: Jon S. Martens, David V. Judge, Jimmy A. Bigelow