Abstract: A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.

Abstract: A power supply system (200) has a QFN leadframe with leads and a pad (201). The pad surface facing a circuit board has a portion recessed with a depth (270) and an outline suitable for attaching side-by-side the sync (210) and the control (220) FET semiconductor chips. The input terminal (220a) of the control FET and the grounded output terminal (210a) of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip (230) is vertically stacked to the opposite pad surface and encapsulated in a packaging compound (290).

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract: A power supply system (200) has a QFN leadframe with leads and a pad (201). The pad surface facing a circuit board has a portion recessed with a depth (270) and an outline suitable for attaching side-by-side the sync (210) and the control (220) FET semiconductor chips. The input terminal (220a) of the control FET and the grounded output terminal (210a) of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip (230) is vertically stacked to the opposite pad surface and encapsulated in a packaging compound (290).

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract: A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.

Abstract: A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.