Abstract: A method for creating constraints for integrated circuit design closure is provided. Design specifications are captured before a design flow is started. The design specifications are checked for compatibility with the design flow. The design specifications are stored in a database. Output transforms are applied to the design specifications to create orthogonal constraint sets which are tuned for both a specific tool and a positional use of the specific tool within the design flow.

Abstract: A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e.g., clock property information, clock domain crossing information, and clock relationship specification. The tool and method embodied therein validates the clocking parameters of the design requirements with the resource definitions and invokes errors if the parameters are not realizable. Once the desired clocking parameters are consistent with the actual clocking parameters, correct physical optimization constraints and timing constraints are generated for the clocks. An iterative process can achieve correct and minimal clocking constraints.

Abstract: A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

Abstract: A method and apparatus are provided for identifying a potential floorplan problem in an integrated circuit layout pattern. The method and apparatus identify a critical timing path in the layout pattern and identify a start point and one or more end points along the timing path. It is then determined whether any of the one or more end points are floor-planned objects. For each end point that is a floor-planned object, the method and apparatus compare a distance between that end point and the start point with a distance threshold to produce a comparison result. A potential floorplan problem can be identified if the distance exceeds the distance threshold.

Abstract: A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path between synchronous clock domains is defined as a false path in the integrated circuit design, then reporting a fatal violation.

Abstract: A clock integration method, tool, and a computer program product that captures, creates, and seamlessly integrates a clock specification to achieve a correct-by-construction design flow of a semiconductor product, such as an ASIC, from a partially manufactured semiconductor platform. The clocking elements of the design flow are combined and displayed to a chip designer in a plurality of context-driven user interfaces and views. Within each view, the details of the clock specification are presented in the context of the information to guide a chip designer to make relevant and correct determinations, e.g., if the context is a high level overview of the logic of the intended semiconductor product, then only the high level parameters, such as source, frequency, path of the clocks signals through the high level modules, etc. are seen. When a chip designer wants more or less detailed information, she/he need only zoom in/zoom out through the plurality of views of the design flow.

Abstract: A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: A footprint based optimal characterization of intellectual property (IP) for more deterministic physical integration. The physical integration characteristics are based upon IP physical integration at an anchor point in a pre-defined IC platform. IP footprint characteristics are identified as fixed, variable or prioritized to each other, and bounding constraints are defined based on a set of characteristics for the IP, the platform characteristics and IC design requirements. The IP is physically synthesized using the bounding constraints. The synthesized IP is tested and the bounding constraints are iteratively modified until the characteristics of the synthesized IP are optimized/captured.

Abstract: A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

Abstract: The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration (“test backplane”) for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the “test backplane”. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the “test backplane”. These pre-exiting test structures may then be connected.

Abstract: A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.