Patents by Inventor Jonathan C. Hall

Jonathan C. Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230137812
    Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
    Type: Application
    Filed: December 31, 2022
    Publication date: May 4, 2023
    Inventors: Andrew T. FORSYTH, Brian J. HICKMANN, Jonathan C. HALL, Christopher J. HUGHES
  • Patent number: 11599362
    Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 7, 2023
    Assignee: INTEL CORPORATION
    Inventors: Andrew T. Forsyth, Brian J. Hickmann, Jonathan C. Hall, Christopher J. Hughes
  • Publication number: 20210406026
    Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
    Type: Application
    Filed: May 10, 2021
    Publication date: December 30, 2021
    Inventors: Andrew T. FORSYTH, Brian J. HICKMANN, Jonathan C. HALL, Christopher J. HUGHES
  • Patent number: 11003455
    Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Andrew T. Forsyth, Brian J. Hickmann, Jonathan C. Hall, Christopher J. Hughes
  • Patent number: 10460185
    Abstract: A system and method for roadside image tracing are described herein. The system includes a camera mounted on a vehicle configured to capture images of objects around the vehicle while driving along a route of a plurality of routes, and processing circuitry. The processing circuitry is configured to receive the captured images from the camera and vehicle parameters including speed, a fuel level, and a mileage, extract objects and locations of the objects within the captured images including information related to driving, determine a route ranking based on the information collected from the objects during one or more trips along each route of the plurality of routes, generate route options based on the route ranking and the vehicle parameters, and transmit route options to a display.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 29, 2019
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Jonathan C. Hall, Tomohiro Matsukawa
  • Patent number: 10414275
    Abstract: An information display system includes a steering wheel including a ring portion and an upper opening region within the ring portion, an instrument cluster arrangement positioned forward of the steering wheel, and an electronic control unit. The instrument cluster arrangement includes a first gauge having a first fixing member on a portion of a boundary of the first gauge, and a second gauge having a second fixing member on a portion of a boundary of the second gauge. The first fixing member and the second fixing member are configured to hold a handheld device placed between the first and second gauges, and the first and second gauges are positioned such that when the handheld device is placed between the first and second gauges the handheld device is visible through the upper opening region.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 17, 2019
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventor: Jonathan C. Hall
  • Patent number: 10387151
    Abstract: Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Jonathan C. Hall, Sailesh Kottapalli, Andrew T. Forsyth
  • Publication number: 20190250921
    Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Andrew T. FORSYTH, Brian J. HICKMANN, Jonathan C. HALL, Christopher J. HUGHES
  • Publication number: 20190236382
    Abstract: A system and method for roadside image tracing are described herein. The system includes a camera mounted on a vehicle configured to capture images of objects around the vehicle while driving along a route of a plurality of routes, and processing circuitry. The processing circuitry is configured to receive the captured images from the camera and vehicle parameters including speed, a fuel level, and a mileage, extract objects and locations of the objects within the captured images including information related to driving, determine a route ranking based on the information collected from the objects during one or more trips along each route of the plurality of routes, generate route options based on the route ranking and the vehicle parameters, and transmit route options to a display.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Applicant: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Jonathan C. HALL, Tomohiro Matsukawa
  • Publication number: 20190193561
    Abstract: An information display system includes a steering wheel including a ring portion and an upper opening region within the ring portion, an instrument cluster arrangement positioned forward of the steering wheel, and an electronic control unit. The instrument cluster arrangement includes a first gauge having a first fixing member on a portion of a boundary of the first gauge, and a second gauge having a second fixing member on a portion of a boundary of the second gauge. The first fixing member and the second fixing member are configured to hold a handheld device placed between the first and second gauges, and the first and second gauges are positioned such that when the handheld device is placed between the first and second gauges the handheld device is visible through the upper opening region.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Applicant: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventor: Jonathan C. Hall
  • Patent number: 10317909
    Abstract: Provided is a method and device for positioning a vehicle attachment point in a vehicle environment. On retrieving a plurality of object parameters relating to an object, a determination is made for a vehicle distance value relative to the vehicle attachment point in order to accommodate an object distance parameter that was retrieved from the plurality of object parameters. A vehicle environment assessment is then made relating to accommodating the physical characteristics of the object and the vehicle associated with the vehicle attachment point. Based on the assessment, vehicle attachment point positional data may be generated for positioning the vehicle attachment point relative to a vehicle environment based on at least the object distance parameter and the vehicle distance value.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: June 11, 2019
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Kameron R. Hurst, Jonathan C. Hall, Cassandra R. Grant, Frankie B. Reed
  • Patent number: 10275257
    Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Andrew T. Forsyth, Brian J. Hickmann, Jonathan C. Hall, Christopher J. Hughes
  • Patent number: 10175990
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Yen-Kuang (Y. K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Patent number: 10133577
    Abstract: A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Jesus Corbal, Dennis R. Bradford, Jonathan C. Hall, Thomas D. Fletcher, Brian J. Hickmann, Dror Markovich, Amit Gradstein
  • Patent number: 10114651
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Yen-Kuang (Y. K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Patent number: 10007620
    Abstract: A processor includes a set associative cache and a cache controller. The cache controller makes an initial association between first and second groups of sampled sets in the cache and first and second cache replacement policies. Follower sets in the cache are initially associated with the more conservative of the two policies. Following cache line insertions in a first epoch, the associations between the groups of sampled sets and cache replacement policies are swapped for the next epoch. If the less conservative policy outperforms the more conservative policy during two consecutive epochs, the follower sets are associated with the less conservative policy for the next epoch. Subsequently, if the more conservative policy outperforms the less conservative policy during any epoch, the follower sets are again associated with the more conservative policy. Performance may be measured based the number of cache misses associated with each policy.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventors: Seth H. Pugsley, Christopher B. Wilkerson, Roger Gramunt, Jonathan C. Hall, Prabhat Jain
  • Publication number: 20180173241
    Abstract: Provided is a method and device for positioning a vehicle attachment point in a vehicle environment. On retrieving a plurality of object parameters relating to an object, a determination is made for a vehicle distance value relative to the vehicle attachment point in order to accommodate an object distance parameter that was retrieved from the plurality of object parameters. A vehicle environment assessment is then made relating to accommodating the physical characteristics of the object and the vehicle associated with the vehicle attachment point. Based on the assessment, vehicle attachment point positional data may be generated for positioning the vehicle attachment point relative to a vehicle environment based on at least the object distance parameter and the vehicle distance value.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Kameron R. Hurst, Jonathan C. Hall, Cassandra R. Grant, Frankie B. Reed
  • Publication number: 20180150301
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Application
    Filed: May 20, 2013
    Publication date: May 31, 2018
    Inventors: Christopher J. Hughes, Yen-Kuang (Y.K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Publication number: 20180129506
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Application
    Filed: January 4, 2018
    Publication date: May 10, 2018
    Inventors: Christopher J. Hughes, Yen-Kuang (Y.K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Publication number: 20180095895
    Abstract: A processor includes a set associative cache and a cache controller. The cache controller makes an initial association between first and second groups of sampled sets in the cache and first and second cache replacement policies. Follower sets in the cache are initially associated with the more conservative of the two policies. Following cache line insertions in a first epoch, the associations between the groups of sampled sets and cache replacement policies are swapped for the next epoch. If the less conservative policy outperforms the more conservative policy during two consecutive epochs, the follower sets are associated with the less conservative policy for the next epoch. Subsequently, if the more conservative policy outperforms the less conservative policy during any epoch, the follower sets are again associated with the more conservative policy. Performance may be measured based the number of cache misses associated with each policy.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Seth H. Pugsley, Christopher B. Wilkerson, Roger Gramunt, Jonathan C. Hall, Prabhat Jain