Abstract: A vehicle information display system and an instrument panel assembly configured to project vehicle information onto the windshield or on a meter panel is provided. The information display system and the instrument panel assembly utilizes a single electronic display to either display vehicle information on the meter panel or to project vehicle information onto the windshield so as to reduce the number of components needed to perform both functions, and thus reduce packaging space. The electronic display and a first panel are rotatably mounted to the first display opening so as to alternatively cover the first display opening, wherein in a first mode of operation the electronic display is disposed within the first display opening and in a second mode of operation the first panel is disposed within the opening and the vehicle information is projected onto the windshield.

Abstract: Embodiments of an under seat capture device are described. Some embodiments include a first chute for aligning below a gap between a center console and a vehicle seat, a first platform component that is coupled to the first chute for receiving an object, and an actuator that is coupled to the first platform component that causes a change in position of the first platform component to guide the object received by the first platform component to a desired location.

Abstract: Embodiments of a retractable storage apparatus are described. Some embodiments include a hinge component, a back support disposed on a first side of the hinge component, and a lower support disposed on the first side of the hinge component. Some embodiments include an anchor component that is disposed on a second side of the hinge component, where when the retractable storage apparatus is disengaged, the back support, the lower support, and the anchor component are substantially coplanar and disposed within a mechanism cavity. Similarly, in some embodiments, in response to receiving a force directed into the mechanism cavity, the retractable storage apparatus is engaged such that the back support and the lower support extend from the mechanism cavity to expose the back support and the lower support and the back support and the lower support rotate on the hinge component to receive a mobile device.

Abstract: An information display system for a vehicle is provided. The information display system includes a steering wheel including a ring portion and a upper opening region within the ring portion, an instrument cluster arrangement positioned forward of the steering wheel and including one or more gauges positioned such that at least a portion of the one or more gauges is visible through the upper opening region of the steering wheel, a holder configured to receive a handheld device, the holder being positioned adjacent to the one or more gauges such that the handheld device being placed on the holder is visible through the upper opening region, and an electronic control unit configured to communicate with the handheld device positioned in the holder to display information associated with the vehicle on the handheld device.

Abstract: A method of an aspect includes receiving an instruction indicating a first source packed memory indices, a second source packed data operation mask, and a destination storage location. Memory indices of the packed memory indices are compared with one another. One or more sets of duplicate memory indices are identified. Data corresponding to each set of duplicate memory indices is loaded only once. The loaded data corresponding to each set of duplicate memory indices is replicated for each of the duplicate memory indices in the set. A packed data result in the destination storage location in response to the instruction. The packed data result includes data elements from memory locations that are indicated by corresponding memory indices of the packed memory indices when not blocked by corresponding elements of the packed data operation mask.

Abstract: An apparatus and method for efficiently managing the architectural state of a processor.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: A vehicle information display system and an instrument panel assembly configured to project vehicle information onto the windshield or on a meter panel is provided. The information display system and the instrument panel assembly utilizes a single electronic display to either display vehicle information on the meter panel or to project vehicle information onto the windshield so as to reduce the number of components needed to perform both functions, and thus reduce packaging space. The electronic display and a first panel are rotatably mounted to the first display opening so as to alternatively cover the first display opening, wherein in a first mode of operation the electronic display is disposed within the first display opening and in a second mode of operation the first panel is disposed within the opening and the vehicle information is projected onto the windshield.

Abstract: Embodiments of a retractable storage apparatus are described. Some embodiments include a hinge component, a back support disposed on a first side of the hinge component, and a lower support disposed on the first side of the hinge component. Some embodiments include an anchor component that is disposed on a second side of the hinge component, where when the retractable storage apparatus is disengaged, the back support, the lower support, and the anchor component are substantially coplanar and disposed within a mechanism cavity. Similarly, in some embodiments, in response to receiving a force directed into the mechanism cavity, the retractable storage apparatus is engaged such that the back support and the lower support extend from the mechanism cavity to expose the back support and the lower support and the back support and the lower support rotate on the hinge component to receive a mobile device.

Abstract: Embodiments of an under seat capture device are described. Some embodiments include a first chute for aligning below a gap between a center console and a vehicle seat, a first platform component that is coupled to the first chute for receiving an object, and an actuator that is coupled to the first platform component that causes a change in position of the first platform component to guide the object received by the first platform component to a desired location.

Abstract: Exemplary aspects are directed toward resolving fault suppression in hardware, which at the same time does not incur a performance hit. For example, when multiple instructions are executing simultaneously, a mask can specify which elements need not be executed. If the mask is disabled, those elements do not need to be executed. A determination is then made as to whether a fault happens in one of the elements that have been disabled. If there is a fault in one of the elements that has been disabled, a state machine re-fetches the instructions in a special mode. More specifically, the state machine determines if the fault is on a disabled element, and if the fault is on a disabled element, then the state machine specifies that the fault should be ignored. If during the first execution there was no mask, if there is an error present during execution, then the element is re-run with the mask to see if the error is a “real” fault.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: Embodiments of systems, methods, and apparatuses for thread selection and reservation station binding are disclosed. In an embodiment, an apparatus includes allocation hardware including reservation station binding logic to bind an operation to one of a plurality of reservation stations. In an embodiment, an apparatus includes thread selection logic to select a thread to be processed by a pipeline stage, wherein the thread selection logic to evaluate a plurality of conditions to select a thread, wherein the conditions include if a thread is active, if a thread has operations in an instruction queue, if a thread has available resources, and if a thread has no known stall.