Abstract: Embodiments herein relate to a semiconductor device which includes one or more voltage regulator (VR) chiplets coupled to a package interposer, where the package interposer includes coaxial magnetic composite core inductors to provide power to one or more load die. In one possible configuration, the one or more VR chiplets are coupled to the bottom side of the package interposer, the bottom side of the package interposer is coupled to the top side of a motherboard, and the one or more load die are coupled to the top side of the package interposer. In another possible configuration, the one or more VR chiplets are coupled to the bottom side of the package interposer, the top side of the package interposer is coupled to the bottom side of a motherboard and the one or more load die are coupled to the top side of the motherboard.

Abstract: Embodiments herein relate to techniques to integrate a capacitive voltage regulator in an integrated circuit (IC) package. The voltage regulator may provide a power supply to one or more load domains in the IC package. The transistors of the voltage regulator may be included on the same die as one or more of the load domains, another die, and/or an interposer of the IC package. The capacitors may be included in the same die as the transistors, in the interposer, in a package layer (e.g., package core), and/or in the same die as one or more of the load domains. Accordingly, the voltage regulator can be integrated close to the relevant load domains, delivering power with short current paths and thereby providing reduced input impedance, output impedance, and associated losses compared with prior techniques. Other embodiments may be described and claimed.

Abstract: Embodiments herein relate to a voltage regular (VR) formed from dies stacked on a package base layer. The VR can include a first part on a first die and a second part on a second die, where the different parts are selected based on characteristics of the respective die such as their voltage domains or technologies. In a capacitor-based VR, an input capacitor and switches subject to a relatively high input voltage can be provided in the first die, while a flying capacitor, output capacitor and switches subject to a relatively low output voltage can be provided in the second die. In an inductor-based VR, an inductor and one or more switches subject to a relatively high input voltage can be provided in the first die, while an output capacitor subject to a relatively low output voltage can be provided in the second die.

Abstract: Embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (VR), external to a package, for supplying current to a compute die in the package. When the required current exceeds a threshold, an additional current source is activated. The additional current source can include a second VR, also external to the package, for supplying current to an integrated voltage regulator (IVR) in the package. The IVR performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first VR is capped at the threshold.

Abstract: Embodiments herein relate to a voltage regular (VR) formed from a first die stacked on a package base layer. The VR can have an inductor-first design in which an inductor is in the package base layer and active circuitry such as switches is in the first die. The inductor receives an input voltage, Vin, directly from the package base layer without the input voltage first entering the first die. The VR can comprise a Kappa VR which includes first and second inductors in the package base layer. The inductors can have asymmetric inductances to improve efficiency. The VR can be cascaded with a set of current multipliers or a Continuously Scalable Conversion Ratio (CSCR) capacitive regulator. Another example implementation includes a switched-inductor-capacitor converter cascaded with a set of switched capacitor current multipliers.

Abstract: Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

Abstract: Embodiments disclosed herein include a coupled inductor. In an embodiment, the coupled inductor comprises a first inductor and a second inductor. In an embodiment, the first inductor can be coupled to the first inductor. In an embodiment, the coupled inductor further comprises a first switch coupled to the first inductor, where the first switch comprises gallium and nitrogen, and a second switch coupled to the second inductor, where the second switch comprises gallium and nitrogen.

Abstract: An apparatus and a method of use thereof for digitally displaying post position numbers above stalls in a game of horse racing. The apparatus includes an array of panels, each panel includes a housing configured to mount to a supporting structure of a stall and an electronic display coupled to the housing. The array of panels can mount such that the electronic displays of the array panels are continuous. Post position numbers can be received remotely through a remote control and can be displayed for each gate.

Abstract: Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

Abstract: A building system for a building including one or more storage devices storing instructions thereon that, when executed by one or more processors, cause the one or more processors to operate one or more pieces of building equipment associated with a building space based on a first operating mode. The instructions cause the one or more processors to receive an indication to update operation of the building space based on an emergency situation and responsive to receiving the indication to update operation of the building space based on the emergency situation, operate the one or more pieces of building equipment based on a second operating mode, wherein the second operating mode defines one or more second parameters for the one or more pieces of building equipment and is adapted to reconfigure the operation of the building space to address or mitigate the emergency situation.

Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

Abstract: Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.

Abstract: A refrigeration system includes a valve and a controller. The valve is configured to control the flow of refrigerant into an evaporator, the refrigerant having an associated liquid setting comprising a temperature and a pressure at which the refrigerant flows through the valve. The controller is operable to adjust the liquid setting, the adjusted liquid setting comprising a temperature and a pressure selected to improve energy efficiency under conditions currently being experienced by the refrigeration system, wherein the controller is operable to adjust the temperature and the pressure simultaneously such that the adjustment does not interfere with operation of the valve.

Abstract: A building system for a building including one or more storage devices storing instructions thereon that, when executed by one or more processors, cause the one or more processors to operate one or more pieces of building equipment associated with a building space based on a first operating mode. The instructions cause the one or more processors to receive an indication to update operation of the building space based on an emergency situation and responsive to receiving the indication to update operation of the building space based on the emergency situation, operate the one or more pieces of building equipment based on a second operating mode, wherein the second operating mode defines one or more second parameters for the one or more pieces of building equipment and is adapted to reconfigure the operation of the building space to address or mitigate the emergency situation.

Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

Abstract: Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.

Abstract: Techniques and mechanisms for mitigating an overshoot of a supply voltage provided with a voltage regulator (VR). In an embodiment, buck converter functionality of a VR is provided with first circuitry comprising a first inductor and first switch circuits variously coupled thereto. Second circuitry of the VR comprises a second inductor and second switch circuits variously coupled thereto. In response to an indication of a voltage overshoot condition, respective states of the first switch circuits and the second switch circuits are configured to enable a conductive path for dissipating energy with the first inductor, the second inductor, and various ones of the first switch circuits and the second switch circuits. In another embodiment, mitigating the voltage overshoot condition comprises alternately toggling between two different configurations of the second switch circuits.

Abstract: In some examples, a voltage protection apparatus includes a circuit to compare an input voltage of a processor to a threshold voltage, and to provide a throttle signal to the processor if the input voltage of the processor droops below the threshold voltage. The processor input voltage can then be set to a lower voltage and the processor power can thus be lowered.

Abstract: A refrigeration system includes a valve and a controller. The valve is configured to control the flow of refrigerant into an evaporator, the refrigerant having an associated liquid setting comprising a temperature and a pressure at which the refrigerant flows through the valve. The controller is operable to adjust the liquid setting, the adjusted liquid setting comprising a temperature and a pressure selected to improve energy efficiency under conditions currently being experienced by the refrigeration system, wherein the controller is operable to adjust the temperature and the pressure simultaneously such that the adjustment does not interfere with operation of the valve.

Abstract: A refrigeration system includes a valve and a controller. The valve is configured to control the flow of refrigerant into an evaporator, the refrigerant having an associated liquid setting comprising a temperature and a pressure at which the refrigerant flows through the valve. The controller is operable to adjust the liquid setting, the adjusted liquid setting comprising a temperature and a pressure selected to improve energy efficiency under conditions currently being experienced by the refrigeration system, wherein the controller is operable to adjust the temperature and the pressure simultaneously such that the adjustment does not interfere with operation of the valve.