Abstract: An active integrated circuit socket includes plural pin sockets receiving corresponding pins of an integrated circuit and plural socket pins making electrical contact with a printed circuit board. At least one active electronic component requiring electrical power for operation connects a pin sockets to a corresponding socket pin. The active electronic component may be a single ended input to differential output driver, a differential input to single ended output driver, a single ended to differential input/output transceiver or a voltage level shifter. These active components may include passive termination resistors. The single ended to differential transceiver may further include an enable input determining the direction of data transmission. This invention may be employed as an electronic system upgrade product including at least two active integrated circuit sockets connected via a flexible sheet including a plurality of electrical conductors connecting differential signal lines.

Abstract: In a method embodiment (10), the method operates a microprocessor (110), and the microprocessor has an instruction set. The method first (11) stores an identifier code uniquely identifying the particular microprocessor in a one-time programmable register. The method second (12) issues to the microprocessor an identifier request instruction from the instruction set. The method then, and in response to the identifier request instruction, provides (18) from the microprocessor an identifier code. Other circuits, systems, and methods are also disclosed and claimed.

Abstract: Circuits, systems, and methods relating to operating a computer system operable in a system manager mode (24). The method includes various steps. The first step (34) occurs during operation of the computer system (10) at a time other than start-up, and receives user power management data from a user of the computer system. The second step (38) stores the user power management data in memory space (30) accessible by the system management mode. The third step (40) accesses the user power management data from the memory space. Finally, the fourth step (42) controls at least one peripheral (14, 16, 18, 20) of the computer system in response to the accessed user power management data.

Abstract: A microprocessor operates in response to microinstructions stored in a read only memory. A patch table stores a indication of patch microinstructions stored in cache memory. This cache memory caches data and/or macroinstructions for the microprocessor. Each new microaddress is compared with the patch table entries. If there in no match, then a multiplexer selects the microinstruction recalled from that microinstruction address within the microinstruction read only memory. If there is a match, then a corresponding patch microinstruction is recalled from the cache memory. The multiplexer selects this patch microinstruction. The microprocessor operates under the control of the selected microinstruction. This technique enables a fix of faulty microinstructions in the field, by supplying the computer user with the patch microinstructions. Using a portion of the cache memory to store the patch microinstructions eliminates any problem with specifying too large or too small a memory for patch microinstructions.

Abstract: An emulation device which enables a functional circuit to support self emulation. A serial scan testability interface has at least first, second and third scan paths, said first scan path being provided for applying digital information to the functional circuit for use in emulation of the functional circuit. A first state machine connected to said second scan path has a first state selected from among a first set of states. A second state machine connected to said third scan path has a second state selected from among a second set of states. The emulation device performs an emulation command based on a combined first state of said first state machine and second state of said second state machine. The state of the first state machine indicates a primary portion of the emulation command denoting an emulation command class. The state of the second state machine indicates a secondary portion of the emulation command consisting of a subtype within the emulation command class.

Abstract: A microprocessor (10) comprising a central processor unit core (12) operable to write information during a write cycle and a cache circuit (18) coupled to the central processor unit core and operable to evict information. The microprocessor further includes a combined storage queue (16) coupled to the central processor unit core and to the cache circuit. The combined storage queue includes a set of logical storage blocks (22c) which is operable to store both information written by the central processor unit core and information evicted by the cache circuit. Other circuits, systems, and methods are also disclosed and claimed.

Abstract: A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected.

Abstract: A method of operating a microprocessor (12). The method first receives (64) a plurality of instructions arranged in a sequence from a first instruction through a last instruction. The method second identifies (66) a branch instruction as one of the plurality of instructions, wherein the branch instruction has a target instruction address. The method third determines two factors for the branch instruction, the first being a prediction value (72) indicating whether or not program flow should pass to the target instruction address, and the second being an accuracy measure (74, 76) indicating accuracy of past ones of the prediction value. The method fourth identifies a data fetching instruction following the branch instruction in the plurality of instructions. Lastly, the method issues a prefetch request (70, 78) for the data fetching instruction in response to the accuracy measure.

Abstract: In a microprocessor embodiment (26), the microprocessor is operable to multi-task a plurality of programs, wherein the plurality of programs include a virtual program (38, 40) operable in a virtual mode and a monitor program (36) in a protected mode. The microprocessor includes an interrupt handling circuit (30) for executing an interrupt handler in response to a hardware interrupt request signal (HIM.cndot.INTR). The microprocessor further includes an interrupt flag bit (IF) set in a like manner in both the virtual mode and the protected mode. The interrupt flag bit is set in a first state to inhibit receipt of the hardware interrupt request signal by the interrupt handling circuit, and the interrupt flag bit is set in a second state to enable receipt of the hardware interrupt request signal by the interrupt handling circuit. The microprocessor further includes a virtual mode control signal (VM.cndot.

Abstract: A processor processes a plurality of instructions according to a disclosed method. First, the method receives (32) an instruction from the plurality of instructions. Second, the method determines (34) whether the received instruction is preceded by an instruction path leading code. Third, the method passes (36 or 38) the received instruction along at least one instruction path in a plurality of instruction paths. Fourth, in response to determining that the received instruction is preceded by an instruction path leading code, the method executes a machine word corresponding to the received instruction and selected from one of the plurality of instruction paths. Specifically, the selected instruction path is selected in response to the instruction path leading code.

Abstract: A microprocessor-based data processing system (2) in which asynchronous bus transactions are performed is disclosed. The disclosed embodiments include one or more microprocessors (5) of the x86-architecture type, compatible with the P54C bus protocol, preferably Pentium-compatible microprocessors, as the central processing units (CPUs) of the system. A CPU (5.sub.r) requests an asynchronous bus transaction, in a first disclosed embodiment, by presenting a combination of control signals that is unused in conventional x86-architecture systems; the controller chipset (27) determines whether the transaction may be performed in an asynchronous manner, and later returns an acknowledge or non-acknowledge code to the requesting CPU (5.sub.r). The microprocessors (5) include certain pins, in this first embodiment, corresponding to conventional Pentium-compatible output pins but which now have receiver circuitry for receiving the acknowledge and non-acknowledge codes, along with the transaction identifier.

Abstract: A circuit (10) for producing a microprogram memory address (16). This circuit includes circuitry (18I, 18J) for selecting a plurality of condition codes. Additionally, the circuit includes logic circuitry (20) for producing a result by performing logic operations using as operands the selected plurality of condition codes. The result of the logic operations forms a first portion (LSB', or LSB' and NLSB') of the microprogram memory address.

Abstract: A microprocessor has an internal cache memory which can cache a mix of normal system memory and system management mode memory. An address translator passes an address unchanged if a system management mode input signal indicates the normal mode. The address translator translates the address to an address range outside a range of addresses occupied by the external memory when in the system management mode. A cache memory is connected to the address translator for caching data with address tags corresponding to an address received from the address translator. The address translator preferably includes an address range comparator comparing the address with a predetermined address range. The address translation may be combined with virtual memory to physical memory address translation. An inverse address translator handles cache line writeback.

Abstract: In a preferred method embodiment, the method operates a microprocessor (36). The method fetches (14) a short backward branch loop (34) of instructions, wherein the short backward branch loop comprises a branch instruction (SSB) and a target instruction (TR) The method also determines that the short backward branch instruction is a short backward branch instruction after fetching it. Still further, the method stores (30) a short backward branch loop of execution unit instructions. This short backward branch loop comprises a branch execution unit instruction (SSB) and a target execution unit instruction (TR). Additionally, without re-fetching the short backward branch loop after the storing step, the method also executes (22) a plurality of iterations of the short backward branch loop of execution unit instructions over a plurality of clock cycles.

Abstract: A programmable logic device, such as a digital signal processor (DSP) (130), having a Euclidean array unit (115; 115') is disclosed. The Euclidean array unit (115; 115') is arranged to perform finite field arithmetic functions useful in determining the greatest common factor among two polynomial series, in a sequential fashion beginning with a highest order pair of operands (A.sub.0, B.sub.0) and proceeding along the sequence. A source register (SRC) receives each pair of operands, and the results are stored in a result register (RES) in reverse order, prior to writing the results in memory. As a result, B result values are stored in the same location as the A input operand, and vice versa. This reversal of memory locations permits successive passes of the Euclidean operation to be carried out with simple incrementing of the starting byte address (SBA) at which the operands are located in memory, thus eliminating the need for large memory shifts.

Abstract: A load target circuit (56) with a plurality of entries (56.sub.1). Each the plurality of entries in the load target circuit comprises a value (ADDRESS TAG) for corresponding the line to a data fetching instruction. Additionally, each load target circuit line also includes a plurality of pointers (POINTER A, POINTER B, POINTER C). Each of the plurality of pointers is for storing a target data address corresponding to an incident of the data fetching instruction.

Abstract: In a method embodiment (34), the method operates a computer system (10) having a type of configuration and including a single integrated circuit microprocessor (24). The microprocessor operates in response to codes and has an instruction set. The method involves various steps, including determining (40) the type of the configuration. In response to the type of the configuration, the method selects (42) a set of patch codes from a plurality of sets of patch codes. The method also issues (54) a patch request instruction from the instruction set, and it stores (56) the selected set of patch codes to a memory space accessible by the microprocessor.

Abstract: A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction.

Abstract: A microprocessor (10) and system (2) including a multi-stream pipeline unit (25) are disclosed. The multi-stream pipeline unit (25) includes individual fetch units (26), instruction caches (16.sub.i), and decoders (34) in separate instruction streams (PROC0, PROC1) or pipelines. A common scheduler (36) is provided to check for dependencies among the instructions from the multiple instruction streams (PROC0, PROC1), and to launch instructions for execution by the various execution units (31, 40, 42, 50), including a microcode unit (47). A common register file (39) includes register banks (70) dedicated to each pipeline, and also a register bank (72) that includes temporary and shared registers available to instructions of either instruction stream (PROC0, PROC1), such as useful in the event of register renaming due to a dependency. Each decoded instruction in the scheduler (36) has an identifier (PROC) indicating the one of the instruction streams (PROC0, PROC1) from which it was issued.

Abstract: Circuits, systems, and methods of operating a processor (110) to process a plurality of instructions, wherein each of the plurality of instructions has a respective sequence number. Further, selected ones of the plurality of instructions are for accessing a non-register memory (18). For each of the selected ones of the plurality of instructions, the method comprises the following steps. One step (24) receives the instruction and another (26) decodes the received instruction. Yet another step (30) stores a plurality of instruction characteristics in a table (14), wherein the characteristics include the sequence number of the instruction, an identifier of the non-register memory to be accessed by the instruction, and a correlation identifier of the non-register memory to a physical register.