Abstract: A method of operating a microprocessor (12) having an on-chip storage resource (100a). The method first receives a data fetching instruction into an instruction pipeline (38) at a first time. The instruction pipeline has a preliminary stage (40), a plurality of stages (42 through 46) following the preliminary stage, and an execution stage (48) following the plurality of stages. The step of receiving a data fetching instruction at the first time comprises receiving the data fetching instruction in the preliminary stage. The method second performs various steps, including fetching a first data quantity (MRU TARGET DATA) for the data fetching instruction to complete the execution stage of the pipeline, completing the execution stage in connection with the data fetching instruction using the first data quantity, and storing the first data quantity in the on-chip storage resource. The method third receives the data fetching instruction into the preliminary stage at a second time (108).

Abstract: A microprocessor includes a control register having a predetermined bit which is unconditionally writable to either a first state or a second state. Additional bits of the control register are writable to either the first or second state when the predetermined bit has the first state. Each additional bit is not writable when the predetermined bit has the second state. The microprocessor further includes at least one circuit controlled by the state of a corresponding one of the additional bits of the control register. The writability of the additional bits is preferably further conditioned upon the state of a machine status register, which is unconditionally writable to either the first state or the second state. A primary AND gate and a secondary AND gate corresponding to each additional bit control the writability of the additional bits.

Abstract: A pipelined microprocessor (10) and system (2) incorporating the same, utilizing combined actual branch history and speculative branch history to predict branches, is disclosed. The microprocessor (10) includes a branch target buffer, or BTB, (56) having a plurality of entries (63) that are associated with previously branching instructions. Each entry (63) has a tag field (TAG) for storing an identifier for its branching instruction based upon the logical address therefore, and a target field (TARGET) for storing the target address for the branching instruction if the branch is taken. Each entry (63) also includes a branch history field (BH), the most-recent bits of which are applied to a pattern history table, or PHT, (53) as an index thereto to retrieve a prediction for the branch.

Abstract: A microprocessor of the superscalar pipelined type, having speculative execution capability, is disclosed. Speculative execution is under the control of a fetch unit having a branch target buffer and a return address stack, each having multiple entries. Each entry includes an address value corresponding to the destination of a branching instruction, and an associated register value, such as a stack pointer. Upon the execution of a subroutine call, the return address and current stack pointer value are stored in the return address stack, to allow for fetching and speculative execution of the sequential instructions following the call in the calling program. Any branching instruction, such as the call, return, or conditional branch, will have an entry included in the branch target buffer; upon fetch of the branch on later passes, speculative execution from the target address can begin using the stack pointer value stored speculatively in the branch target buffer in association with the target address.

Abstract: A microprocessor (26) may multi-task a plurality of programs, and those programs include a virtual program (38 or 40) operable in a virtual mode and a monitor program (34) operable using protected mode semantics. The microprocessor includes input circuitry (INTR) for receiving an external interrupt request signal corresponding to an external interrupt directed to the virtual program, and additional input circuitry (INT#0-7) for receiving an external interrupt number corresponding to the external interrupt directed to the virtual program. The microprocessor further includes an interrupt handling circuit (30) comprising circuitry for identifying an interrupt vector and presenting an interrupt corresponding to the external interrupt request number. Lastly, the microprocessor includes control circuitry (28) coupled to the interrupt handling circuit.

Abstract: A processor embodiment comprises a microprogram memory circuit (12) comprising a number of separately energizable banks (14a, 14b). Each of the number of separately energizable banks is operable to concurrently output at least one microinstruction. The processor further comprises circuitry for forming a microaddress for addressing the microprogram memory. This circuitry includes circuitry (26, 28) for identifying a value of a first bit (A0) and of a second bit (A1), and the microaddress comprises the first bit, the second bit, and a plurality of main bits (20c). Further, the processor includes circuitry for selectively energizing (24, 13a, 13b) a subset of the separately energizable banks in response to the value of the first bit, and the subset is less than the number of separately energizable banks. Still further, the processor includes circuitry (16) for outputting a first set of microinstructions from the subset of the separately energizable banks.

Abstract: Circuits, systems, and methods relating to processor which processes a plurality of sequentially arranged instructions. In the method, one method step (10) receives into a processor pipeline an instruction from the plurality of sequentially arranged instructions. Another step (12) determines whether the received instruction comprises a short forward branch instruction. If the received instruction comprises a short forward branch instruction, the method (14) issues a detection signal and (16) issues a condition signal representing whether or not the condition of the short forward branch instruction is satisfied. Continuing, the method (18) receives into the processor pipeline a first group of instructions of the plurality of sequentially arranged instructions, where each is between the short forward branch instruction and the target instruction.